1 from nmigen
import Module
, Signal
2 from nmigen
.cli
import main
5 """ The purpose of this Module is to centralize the parsing of Page
6 Table Entries (PTE) into one module to prevent common mistakes
7 and duplication of code. The control bits are parsed out for
10 This module parses according to the standard PTE given by the
11 Volume II: RISC-V Privileged Architectures V1.10 Pg 60.
12 The Address Space IDentifier (ASID) is appended to the MSB of the input
13 and is parsed out as such.
15 An valid input Signal would be:
19 The output PTE value will include the control bits.
21 def __init__(self
, asid_size
, pte_size
):
23 * asid_size: (bit count) The size of the asid to be processed
24 * pte_size: (bit count) The size of the pte to be processed
27 * d The Dirty bit from the PTE portion of i
28 * a The Accessed bit from the PTE portion of i
29 * g The Global bit from the PTE portion of i
30 * u The User Mode bit from the PTE portion of i
31 * xwr The Execute/Write/Read bit from the PTE portion of i
32 * v The Valid bit from the PTE portion of i
33 * asid The asid portion of i
34 * pte The pte portion of i
37 self
.asid_start
= pte_size
38 self
.asid_end
= pte_size
+ asid_size
41 self
.i
= Signal(asid_size
+ pte_size
)
44 self
.d
= Signal(1) # Dirty bit (From pte)
45 self
.a
= Signal(1) # Accessed bit (From pte)
46 self
.g
= Signal(1) # Global Access (From pte)
47 self
.u
= Signal(1) # User Mode (From pte)
48 self
.xwr
= Signal(3) # Execute Read Write (From pte)
49 self
.v
= Signal(1) # Valid (From pte)
50 self
.asid
= Signal(asid_size
) # Associated Address Space IDentifier
51 self
.pte
= Signal(pte_size
) # Full Page Table Entry
53 def elaborate(self
, platform
=None):
55 # Pull out all control bites from PTE
61 self
.xwr
.eq(self
.i
[1:4]),
64 m
.d
.comb
+= self
.asid
.eq(self
.i
[self
.asid_start
:self
.asid_end
])
65 m
.d
.comb
+= self
.pte
.eq(self
.i
[0:self
.asid_start
])