1 from nmigen
.compat
.sim
import run_simulation
3 from TLB
.PteEntry
import PteEntry
5 from TestUtil
.test_helper
import assert_op
11 def check_dirty(dut
, d
, op
):
13 assert_op("Dirty", out_d
, d
, op
)
15 def check_accessed(dut
, a
, op
):
17 assert_op("Accessed", out_a
, a
, op
)
19 def check_global(dut
, o
, op
):
21 assert_op("Global", out
, o
, op
)
23 def check_user(dut
, o
, op
):
25 assert_op("User Mode", out
, o
, op
)
27 def check_xwr(dut
, o
, op
):
29 assert_op("XWR", out
, o
, op
)
31 def check_asid(dut
, o
, op
):
33 assert_op("ASID", out
, o
, op
)
35 def check_pte(dut
, o
, op
):
37 assert_op("ASID", out
, o
, op
)
39 def check_valid(dut
, v
, op
):
41 assert_op("Valid", out_v
, v
, op
)
43 def check_all(dut
, d
, a
, g
, u
, xwr
, v
, asid
, pte
):
44 yield from check_dirty(dut
, d
, 0)
45 yield from check_accessed(dut
, a
, 0)
46 yield from check_global(dut
, g
, 0)
47 yield from check_user(dut
, u
, 0)
48 yield from check_xwr(dut
, xwr
, 0)
49 yield from check_asid(dut
, asid
, 0)
50 yield from check_pte(dut
, pte
, 0)
51 yield from check_valid(dut
, v
, 0)
54 # 80 bits represented. Ignore the MSB as it will be truncated
55 # ASID is bits first 4 hex values (bits 64 - 78)
57 i
= 0x7FFF0000000000000031
65 pte
= 0x0000000000000031
66 yield from set_entry(dut
, i
)
67 yield from check_all(dut
, dirty
, access
, glob
, user
, xwr
, valid
, asid
, pte
)
69 i
= 0x0FFF00000000000000FF
77 pte
= 0x00000000000000FF
78 yield from set_entry(dut
, i
)
79 yield from check_all(dut
, dirty
, access
, glob
, user
, xwr
, valid
, asid
, pte
)
81 i
= 0x0721000000001100001F
89 pte
= 0x000000001100001F
90 yield from set_entry(dut
, i
)
91 yield from check_all(dut
, dirty
, access
, glob
, user
, xwr
, valid
, asid
, pte
)
97 dut
= PteEntry(15, 64);
98 run_simulation(dut
, tbench(dut
), vcd_name
="Waveforms/test_pte_entry.vcd")
99 print("PteEntry Unit Test Success")
101 if __name__
== "__main__":