1 from nmigen
import Module
, Signal
2 from nmigen
.cli
import main
, verilog
4 from fpbase
import FPNum
, FPOp
, Overflow
, FPBase
9 def __init__(self
, width
):
13 self
.in_a
= FPOp(width
)
14 self
.in_b
= FPOp(width
)
15 self
.out_z
= FPOp(width
)
17 def get_fragment(self
, platform
=None):
18 """ creates the HDL code-fragment for FPMUL
25 z
= FPNum(self
.width
, 24)
27 tot
= Signal(28) # sticky/round/guard bits, 23 result, 1 overflow
33 with m
.State("get_a"):
35 m
.d
.sync
+= s
.in_a
.ack
.eq(1)
36 with m
.If(s
.in_a
.ack
& in_a
.stb
):
51 if (s_input_a_ack && input_a_stb) begin
61 if (s_input_b_ack && input_b_stb) begin
72 a_e <= a[30 : 23] - 127;
73 b_e <= b[30 : 23] - 127;
76 state <= special_cases;
81 //if a is NaN or b is NaN return NaN
82 if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
88 //if a is inf return inf
89 end else if (a_e == 128) begin
93 //if b is zero return NaN
94 if (($signed(b_e) == -127) && (b_m == 0)) begin
101 //if b is inf return inf
102 end else if (b_e == 128) begin
106 //if a is zero return NaN
107 if (($signed(a_e) == -127) && (a_m == 0)) begin
114 //if a is zero return zero
115 end else if (($signed(a_e) == -127) && (a_m == 0)) begin
120 //if b is zero return zero
121 end else if (($signed(b_e) == -127) && (b_m == 0)) begin
127 //Denormalised Number
128 if ($signed(a_e) == -127) begin
133 //Denormalised Number
134 if ($signed(b_e) == -127) begin
139 state <= normalise_a;
146 state <= normalise_b;
166 z_e <= a_e + b_e + 1;
167 product <= a_m * b_m * 4;
173 z_m <= product[49:26];
174 guard <= product[25];
175 round_bit <= product[24];
176 sticky <= (product[23:0] != 0);
177 state <= normalise_1;
182 if (z_m[23] == 0) begin
189 state <= normalise_2;
195 if ($signed(z_e) < -126) begin
200 sticky <= sticky | round_bit;
208 if (guard && (round_bit | sticky | z_m[0])) begin
210 if (z_m == 24'hffffff) begin
219 z[22 : 0] <= z_m[22:0];
220 z[30 : 23] <= z_e[7:0] + 127;
222 if ($signed(z_e) == -126 && z_m[23] == 0) begin
225 //if overflow occurs, return inf
226 if ($signed(z_e) > 127) begin
238 if (s_output_z_stb && output_z_ack) begin