1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Signal
6 from nmigen
.cli
import main
, verilog
7 from fpbase
import FPState
10 class FPPutZ(FPState
):
12 def __init__(self
, state
, in_z
, out_z
, in_mid
, out_mid
, to_state
=None):
13 FPState
.__init
__(self
, state
)
16 self
.to_state
= to_state
20 self
.out_mid
= out_mid
23 if self
.in_mid
is not None:
24 m
.d
.sync
+= self
.out_mid
.eq(self
.in_mid
)
26 self
.out_z
.z
.v
.eq(self
.in_z
)
28 with m
.If(self
.out_z
.z
.o_valid
& self
.out_z
.z
.i_ready_test
):
29 m
.d
.sync
+= self
.out_z
.z
.o_valid
.eq(0)
30 m
.next
= self
.to_state
32 m
.d
.sync
+= self
.out_z
.z
.o_valid
.eq(1)
35 class FPPutZIdx(FPState
):
37 def __init__(self
, state
, in_z
, out_zs
, in_mid
, to_state
=None):
38 FPState
.__init
__(self
, state
)
41 self
.to_state
= to_state
47 outz_stb
= Signal(reset_less
=True)
48 outz_ack
= Signal(reset_less
=True)
49 m
.d
.comb
+= [outz_stb
.eq(self
.out_zs
[self
.in_mid
].o_valid
),
50 outz_ack
.eq(self
.out_zs
[self
.in_mid
].i_ready_test
),
53 self
.out_zs
[self
.in_mid
].v
.eq(self
.in_z
.v
)
55 with m
.If(outz_stb
& outz_ack
):
56 m
.d
.sync
+= self
.out_zs
[self
.in_mid
].o_valid
.eq(0)
57 m
.next
= self
.to_state
59 m
.d
.sync
+= self
.out_zs
[self
.in_mid
].o_valid
.eq(1)