1 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Array
2 from nmigen
.cli
import main
, verilog
4 from nmigen_add_experiment
import FPADD
5 from rstation_row
import ReservationStationRow
11 def __init__(self
, width
, num_units
):
14 * width: bit-width of IEEE754. supported: 16, 32, 64
15 * num_units: number of Reservation Stations
20 bsz
= int(log(width
) / log(2))
21 for i
in range(num_units
):
23 rs
= ReservationStationRow(width
, mid
)
28 def elaborate(self
, platform
=None):
29 """ creates the HDL code-fragment for ReservationStationRow
36 if __name__
== "__main__":
37 rs
= ReservationStationRow(width
=32, id_wid
=Const(1,4)
38 main(alu
, ports
=[rs
.in_a
, rs
.in_b
, rs
.out_z
]
40 # works... but don't use, just do "python fname.py convert -t v"
41 #print (verilog.convert(alu, ports=[
42 # ports=alu.in_a.ports() + \
43 # alu.in_b.ports() + \