1 """ Combinatorial Multi-input and Multi-output multiplexer blocks
2 conforming to Pipeline API
4 Multi-input is complex because if any one input is ready, the output
5 can be ready, and the decision comes from a separate module.
7 Multi-output is simple (pretty much identical to UnbufferedPipeline),
8 and the selection is just a mux. The only proviso (difference) being:
9 the outputs not being selected have to have their ready_o signals
14 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Array
, Elaboratable
15 from nmigen
.cli
import verilog
, rtlil
16 from nmigen
.lib
.coding
import PriorityEncoder
17 from nmigen
.hdl
.rec
import Record
, Layout
19 from collections
.abc
import Sequence
21 from example_buf_pipe
import eq
, NextControl
, PrevControl
, ExampleStage
24 class MultiInControlBase(Elaboratable
):
25 """ Common functions for Pipeline API
27 def __init__(self
, in_multi
=None, p_len
=1):
28 """ Multi-input Control class. Conforms to same API as ControlBase...
29 mostly. has additional indices to the *multiple* input stages
31 * p: contains ready/valid to the previous stages PLURAL
32 * n: contains ready/valid to the next stage
35 * add data_i members to PrevControl and
36 * add data_o member to NextControl
38 # set up input and output IO ACK (prev/next ready/valid)
40 for i
in range(p_len
):
41 p
.append(PrevControl(in_multi
))
43 self
.n
= NextControl()
45 def connect_to_next(self
, nxt
, p_idx
=0):
46 """ helper function to connect to the next stage data/valid/ready.
48 return self
.n
.connect_to_next(nxt
.p
[p_idx
])
50 def _connect_in(self
, prev
, idx
=0, prev_idx
=None):
51 """ helper function to connect stage to an input source. do not
52 use to connect stage-to-stage!
55 return self
.p
[idx
]._connect
_in
(prev
.p
)
56 return self
.p
[idx
]._connect
_in
(prev
.p
[prev_idx
])
58 def _connect_out(self
, nxt
):
59 """ helper function to connect stage to an output source. do not
60 use to connect stage-to-stage!
63 return self
.n
._connect
_out
(nxt
.n
)
64 return self
.n
._connect
_out
(nxt
.n
)
66 def set_input(self
, i
, idx
=0):
67 """ helper function to set the input data
69 return eq(self
.p
[idx
].data_i
, i
)
71 def elaborate(self
, platform
):
73 for i
, p
in enumerate(self
.p
):
74 setattr(m
.submodules
, "p%d" % i
, p
)
75 m
.submodules
.n
= self
.n
87 class MultiOutControlBase(Elaboratable
):
88 """ Common functions for Pipeline API
90 def __init__(self
, n_len
=1, in_multi
=None):
91 """ Multi-output Control class. Conforms to same API as ControlBase...
92 mostly. has additional indices to the multiple *output* stages
93 [MultiInControlBase has multiple *input* stages]
95 * p: contains ready/valid to the previou stage
96 * n: contains ready/valid to the next stages PLURAL
99 * add data_i member to PrevControl and
100 * add data_o members to NextControl
103 # set up input and output IO ACK (prev/next ready/valid)
104 self
.p
= PrevControl(in_multi
)
106 for i
in range(n_len
):
107 n
.append(NextControl())
110 def connect_to_next(self
, nxt
, n_idx
=0):
111 """ helper function to connect to the next stage data/valid/ready.
113 return self
.n
[n_idx
].connect_to_next(nxt
.p
)
115 def _connect_in(self
, prev
, idx
=0):
116 """ helper function to connect stage to an input source. do not
117 use to connect stage-to-stage!
119 return self
.n
[idx
]._connect
_in
(prev
.p
)
121 def _connect_out(self
, nxt
, idx
=0, nxt_idx
=None):
122 """ helper function to connect stage to an output source. do not
123 use to connect stage-to-stage!
126 return self
.n
[idx
]._connect
_out
(nxt
.n
)
127 return self
.n
[idx
]._connect
_out
(nxt
.n
[nxt_idx
])
129 def elaborate(self
, platform
):
131 m
.submodules
.p
= self
.p
132 for i
, n
in enumerate(self
.n
):
133 setattr(m
.submodules
, "n%d" % i
, n
)
136 def set_input(self
, i
):
137 """ helper function to set the input data
139 return eq(self
.p
.data_i
, i
)
150 class CombMultiOutPipeline(MultiOutControlBase
):
151 """ A multi-input Combinatorial block conforming to the Pipeline API
155 p.data_i : stage input data (non-array). shaped according to ispec
156 n.data_o : stage output data array. shaped according to ospec
159 def __init__(self
, stage
, n_len
, n_mux
):
160 MultiOutControlBase
.__init
__(self
, n_len
=n_len
)
164 # set up the input and output data
165 self
.p
.data_i
= stage
.ispec() # input type
166 for i
in range(n_len
):
167 self
.n
[i
].data_o
= stage
.ospec() # output type
169 def elaborate(self
, platform
):
170 m
= MultiOutControlBase
.elaborate(self
, platform
)
172 if hasattr(self
.n_mux
, "elaborate"): # TODO: identify submodule?
173 m
.submodules
+= self
.n_mux
175 # need buffer register conforming to *input* spec
176 r_data
= self
.stage
.ispec() # input type
177 if hasattr(self
.stage
, "setup"):
178 self
.stage
.setup(m
, r_data
)
180 # multiplexer id taken from n_mux
181 mid
= self
.n_mux
.m_id
184 p_valid_i
= Signal(reset_less
=True)
185 pv
= Signal(reset_less
=True)
186 m
.d
.comb
+= p_valid_i
.eq(self
.p
.valid_i_test
)
187 m
.d
.comb
+= pv
.eq(self
.p
.valid_i
& self
.p
.ready_o
)
189 # all outputs to next stages first initialised to zero (invalid)
190 # the only output "active" is then selected by the muxid
191 for i
in range(len(self
.n
)):
192 m
.d
.comb
+= self
.n
[i
].valid_o
.eq(0)
193 data_valid
= self
.n
[mid
].valid_o
194 m
.d
.comb
+= self
.p
.ready_o
.eq(~data_valid | self
.n
[mid
].ready_i
)
195 m
.d
.comb
+= data_valid
.eq(p_valid_i | \
196 (~self
.n
[mid
].ready_i
& data_valid
))
198 m
.d
.comb
+= eq(r_data
, self
.p
.data_i
)
199 m
.d
.comb
+= eq(self
.n
[mid
].data_o
, self
.stage
.process(r_data
))
204 class CombMultiInPipeline(MultiInControlBase
):
205 """ A multi-input Combinatorial block conforming to the Pipeline API
209 p.data_i : StageInput, shaped according to ispec
211 p.data_o : StageOutput, shaped according to ospec
213 r_data : input_shape according to ispec
214 A temporary (buffered) copy of a prior (valid) input.
215 This is HELD if the output is not ready. It is updated
219 def __init__(self
, stage
, p_len
, p_mux
):
220 MultiInControlBase
.__init
__(self
, p_len
=p_len
)
224 # set up the input and output data
225 for i
in range(p_len
):
226 self
.p
[i
].data_i
= stage
.ispec() # input type
227 self
.n
.data_o
= stage
.ospec()
229 def elaborate(self
, platform
):
230 m
= MultiInControlBase
.elaborate(self
, platform
)
232 m
.submodules
+= self
.p_mux
234 # need an array of buffer registers conforming to *input* spec
240 for i
in range(p_len
):
241 r
= self
.stage
.ispec() # input type
243 data_valid
.append(Signal(name
="data_valid", reset_less
=True))
244 p_valid_i
.append(Signal(name
="p_valid_i", reset_less
=True))
245 n_ready_in
.append(Signal(name
="n_ready_in", reset_less
=True))
246 if hasattr(self
.stage
, "setup"):
247 self
.stage
.setup(m
, r
)
249 r_data
= Array(r_data
)
250 p_valid_i
= Array(p_valid_i
)
251 n_ready_in
= Array(n_ready_in
)
252 data_valid
= Array(data_valid
)
254 nirn
= Signal(reset_less
=True)
255 m
.d
.comb
+= nirn
.eq(~self
.n
.ready_i
)
256 mid
= self
.p_mux
.m_id
257 for i
in range(p_len
):
258 m
.d
.comb
+= data_valid
[i
].eq(0)
259 m
.d
.comb
+= n_ready_in
[i
].eq(1)
260 m
.d
.comb
+= p_valid_i
[i
].eq(0)
261 m
.d
.comb
+= self
.p
[i
].ready_o
.eq(0)
262 m
.d
.comb
+= p_valid_i
[mid
].eq(self
.p_mux
.active
)
263 m
.d
.comb
+= self
.p
[mid
].ready_o
.eq(~data_valid
[mid
] | self
.n
.ready_i
)
264 m
.d
.comb
+= n_ready_in
[mid
].eq(nirn
& data_valid
[mid
])
265 anyvalid
= Signal(i
, reset_less
=True)
267 for i
in range(p_len
):
268 av
.append(data_valid
[i
])
270 m
.d
.comb
+= self
.n
.valid_o
.eq(anyvalid
.bool())
271 m
.d
.comb
+= data_valid
[mid
].eq(p_valid_i
[mid
] | \
272 (n_ready_in
[mid
] & data_valid
[mid
]))
274 for i
in range(p_len
):
275 vr
= Signal(reset_less
=True)
276 m
.d
.comb
+= vr
.eq(self
.p
[i
].valid_i
& self
.p
[i
].ready_o
)
278 m
.d
.comb
+= eq(r_data
[i
], self
.p
[i
].data_i
)
280 m
.d
.comb
+= eq(self
.n
.data_o
, self
.stage
.process(r_data
[mid
]))
285 class CombMuxOutPipe(CombMultiOutPipeline
):
286 def __init__(self
, stage
, n_len
):
287 # HACK: stage is also the n-way multiplexer
288 CombMultiOutPipeline
.__init
__(self
, stage
, n_len
=n_len
, n_mux
=stage
)
290 # HACK: n-mux is also the stage... so set the muxid equal to input mid
291 stage
.m_id
= self
.p
.data_i
.mid
295 class InputPriorityArbiter(Elaboratable
):
296 """ arbitration module for Input-Mux pipe, baed on PriorityEncoder
298 def __init__(self
, pipe
, num_rows
):
300 self
.num_rows
= num_rows
301 self
.mmax
= int(log(self
.num_rows
) / log(2))
302 self
.m_id
= Signal(self
.mmax
, reset_less
=True) # multiplex id
303 self
.active
= Signal(reset_less
=True)
305 def elaborate(self
, platform
):
308 assert len(self
.pipe
.p
) == self
.num_rows
, \
309 "must declare input to be same size"
310 pe
= PriorityEncoder(self
.num_rows
)
311 m
.submodules
.selector
= pe
313 # connect priority encoder
315 for i
in range(self
.num_rows
):
316 p_valid_i
= Signal(reset_less
=True)
317 m
.d
.comb
+= p_valid_i
.eq(self
.pipe
.p
[i
].valid_i_test
)
318 in_ready
.append(p_valid_i
)
319 m
.d
.comb
+= pe
.i
.eq(Cat(*in_ready
)) # array of input "valids"
320 m
.d
.comb
+= self
.active
.eq(~pe
.n
) # encoder active (one input valid)
321 m
.d
.comb
+= self
.m_id
.eq(pe
.o
) # output one active input
326 return [self
.m_id
, self
.active
]
330 class PriorityCombMuxInPipe(CombMultiInPipeline
):
331 """ an example of how to use the combinatorial pipeline.
334 def __init__(self
, stage
, p_len
=2):
335 p_mux
= InputPriorityArbiter(self
, p_len
)
336 CombMultiInPipeline
.__init
__(self
, stage
, p_len
, p_mux
)
339 if __name__
== '__main__':
341 dut
= PriorityCombMuxInPipe(ExampleStage
)
342 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
343 with
open("test_combpipe.il", "w") as f
: