src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main
   7
   8
   9 class FPADD:
  10     def __init__(self, width):
  11         self.width = width
  12
  13         self.in_a     = Signal(width)
  14         self.in_a_stb = Signal()
  15         self.in_a_ack = Signal()
  16
  17         self.in_b     = Signal(width)
  18         self.in_b_stb = Signal()
  19         self.in_b_ack = Signal()
  20
  21         self.out_z     = Signal(width)
  22         self.out_z_stb = Signal()
  23         self.out_z_ack = Signal()
  24
  25         s_out_z_stb  = Signal()
  26         s_out_z      = Signal(width)
  27         s_in_a_ack   = Signal()
  28         s_in_b_ack   = Signal()
  29
  30     def get_fragment(self, platform):
  31         m = Module()
  32
  33         # Latches
  34         a = Signal(self.width)
  35         b = Signal(self.width)
  36         z = Signal(self.width)
  37
  38         # Mantissa
  39         a_m = Signal(27) # ??? seems to be 1 bit extra??
  40         b_m = Signal(27) # ??? seems to be 1 bit extra??
  41         z_m = Signal(24)
  42
  43         # Exponent
  44         a_e = Signal(10)
  45         b_e = Signal(10)
  46         z_e = Signal(10)
  47
  48         # Sign
  49         a_s = Signal()
  50         b_s = Signal()
  51         z_s = Signal()
  52
  53         guard = Signal()
  54         round_bit = Signal()
  55         sticky = Signal()
  56
  57         tot = Signal(28)
  58
  59         with m.FSM() as fsm:
  60
  61             # ******
  62             # gets operand a
  63
  64             with m.State("get_a"):
  65                 with m.If((self.in_a_ack) & (self.in_a_stb)):
  66                     m.next = "get_b"
  67                     m.d.sync += [
  68                         a.eq(self.in_a),
  69                         self.in_a_ack.eq(0)
  70                     ]
  71                 with m.Else():
  72                     m.d.sync += self.in_a_ack.eq(1)
  73
  74             # ******
  75             # gets operand b
  76
  77             with m.State("get_b"):
  78                 with m.If((self.in_b_ack) & (self.in_b_stb)):
  79                     m.next = "get_a"
  80                     m.d.sync += [
  81                         b.eq(self.in_b),
  82                         self.in_b_ack.eq(0)
  83                     ]
  84                 with m.Else():
  85                     m.d.sync += self.in_b_ack.eq(1)
  86
  87             # ******
  88             # unpacks operands into sign, mantissa and exponent
  89
  90             with m.State("unpack"):
  91                 m.next = "special_cases"
  92                 m.d.sync += [
  93                     # mantissa
  94                     a_m.eq(Cat(0, 0, 0, a[0:23])),
  95                     b_m.eq(Cat(0, 0, 0, b[0:23])),
  96                     # exponent (take off exponent bias, here)
  97                     a_e.eq(Cat(a[23:31]) - 127),
  98                     b_e.eq(Cat(b[23:31]) - 127),
  99                     # sign
 100                     a_s.eq(Cat(a[31])),
 101                     b_s.eq(Cat(b[31]))
 102                 ]
 103
 104             # ******
 105             # special cases: NaNs, infs, zeros, denormalised
 106
 107             with m.State("special_cases"):
 108
 109                 # if a is NaN or b is NaN return NaN
 110                 with m.If(((a_e == 128) & (a_m != 0)) | \
 111                           ((b_e == 128) & (b_m != 0))):
 112                     m.next = "put_z"
 113                     m.d.sync += [
 114                           z[31].eq(1),      # sign: 1
 115                           z[23:31].eq(255), # exp: 0b11111...
 116                           z[22].eq(1),      # mantissa top bit: 1
 117                           z[0:22].eq(0)     # mantissa rest: 0b0000...
 118                     ]
 119
 120                 # if a is inf return inf (or NaN)
 121                 with m.Elif(a_e == 128):
 122                     m.next = "put_z"
 123                     m.d.sync += [
 124                         z[31].eq(a_s),    # sign: a_s
 125                         z[23:31].eq(255), # exp: 0b11111...
 126                         z[0:23].eq(0)     # mantissa rest: 0b0000...
 127                     ]
 128                     # if a is inf and signs don't match return NaN
 129                     with m.If((b_e == 128) & (a_s != b_s)):
 130                         m.d.sync += [
 131                           z[31].eq(b_s),    # sign: b_s
 132                           z[23:31].eq(255), # exp: 0b11111...
 133                           z[22].eq(1),      # mantissa top bit: 1
 134                           z[0:22].eq(0)     # mantissa rest: 0b0000...
 135                         ]
 136                 # if b is inf return inf
 137                 with m.Elif(b_e == 128):
 138                     m.next = "put_z"
 139                     m.d.sync += [
 140                         z[31].eq(b_s),    # sign: b_s
 141                         z[23:31].eq(255), # exp: 0b11111...
 142                         z[0:23].eq(0)     # mantissa rest: 0b0000...
 143                     ]
 144
 145                 # if a is zero and b zero return signed-a/b
 146                 with m.Elif(((a_e == -127) & (a_m == 0)) & \
 147                             ((b_e == -127) & (b_m == 0))):
 148                     m.next = "put_z"
 149                     m.d.sync += [
 150                         z[31].eq(a_s & b_s),         # sign: a/b_s
 151                         z[23:31].eq(b_e[0:8] + 127), # exp: b_e (plus bias)
 152                         z[0:23].eq(b_m[3:26])        # mantissa: b_m top bits
 153                     ]
 154
 155                 # if a is zero return b
 156                 with m.Elif((a_e == -127) & (a_m == 0)):
 157                     m.next = "put_z"
 158                     m.d.sync += [
 159                         z[31].eq(b_s),               # sign: a/b_s
 160                         z[23:31].eq(b_e[0:8] + 127), # exp: b_e (plus bias)
 161                         z[0:23].eq(b_m[3:26])        # mantissa: b_m top bits
 162                     ]
 163
 164                 # if b is zero return a
 165                 with m.Elif((b_e == -127) & (b_m == 0)):
 166                     m.next = "put_z"
 167                     m.d.sync += [
 168                         z[31].eq(a_s),               # sign: a/b_s
 169                         z[23:31].eq(a_e[0:8] + 127), # exp: a_e (plus bias)
 170                         z[0:23].eq(a_m[3:26])        # mantissa: a_m top bits
 171                     ]
 172
 173                 # Denormalised Number checks
 174                 with m.Else():
 175                     m.next = "align"
 176                     # denormalise a check
 177                     with m.If(a_e == -127):
 178                         m.d.sync += a_e.eq(-126) # limit a exponent
 179                     with m.Else():
 180                         m.d.sync += a_m[26].eq(1) # set highest mantissa bit
 181                     # denormalise b check
 182                     with m.If(b_e == -127):
 183                         m.d.sync += b_e.eq(-126) # limit b exponent
 184                     with m.Else():
 185                         m.d.sync += b_m[26].eq(1) # set highest mantissa bit
 186
 187                 # First stage of add
 188                 with m.State("add_0"):
 189                     m.next = "add_1"
 190                     m.d.sync += z_e.eq(a_e)
 191                     with m.If(a_s == b_s):
 192                         m.d.sync += [
 193                             tot.eq(a_m + b_m),
 194                             z_s.eq(a_s)
 195                         ]
 196                     with m.Else(a_m >= b_m):
 197                         m.d.sync += [
 198                             tot.eq(a_m - b_m),
 199                             z_s.eq(a_s)
 200                         ]
 201                     with m.Else():
 202                         m.sync += [
 203                             tot.eq(b_m - a_m),
 204                             z_s.eq(b_s)
 205                     ]
 206         return m
 207
 208 """
 209   always @(posedge clk)
 210   begin
 211
 212     case(state)
 213
 214       get_a:
 215       begin
 216         s_in_a_ack <= 1;
 217         if (s_in_a_ack && in_a_stb) begin
 218           a <= in_a;
 219           s_in_a_ack <= 0;
 220           state <= get_b;
 221         end
 222       end
 223
 224       get_b:
 225       begin
 226         s_in_b_ack <= 1;
 227         if (s_in_b_ack && in_b_stb) begin
 228           b <= in_b;
 229           s_in_b_ack <= 0;
 230           state <= unpack;
 231         end
 232       end
 233
 234       unpack:
 235       begin
 236         a_m <= {a[22 : 0], 3'd0};
 237         b_m <= {b[22 : 0], 3'd0};
 238         a_e <= a[30 : 23] - 127;
 239         b_e <= b[30 : 23] - 127;
 240         a_s <= a[31];
 241         b_s <= b[31];
 242         state <= special_cases;
 243       end
 244
 245       special_cases:
 246       begin
 247         //if a is NaN or b is NaN return NaN
 248         if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
 249           z[31] <= 1;
 250           z[30:23] <= 255;
 251           z[22] <= 1;
 252           z[21:0] <= 0;
 253           state <= put_z;
 254         //if a is inf return inf
 255         end else if (a_e == 128) begin
 256           z[31] <= a_s;
 257           z[30:23] <= 255;
 258           z[22:0] <= 0;
 259           //if a is inf and signs don't match return nan
 260           if ((b_e == 128) && (a_s != b_s)) begin
 261               z[31] <= b_s;
 262               z[30:23] <= 255;
 263               z[22] <= 1;
 264               z[21:0] <= 0;
 265           end
 266           state <= put_z;
 267         //if b is inf return inf
 268         end else if (b_e == 128) begin
 269           z[31] <= b_s;
 270           z[30:23] <= 255;
 271           z[22:0] <= 0;
 272           state <= put_z;
 273         //if a is zero return b
 274         end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
 275           z[31] <= a_s & b_s;
 276           z[30:23] <= b_e[7:0] + 127;
 277           z[22:0] <= b_m[26:3];
 278           state <= put_z;
 279         //if a is zero return b
 280         end else if (($signed(a_e) == -127) && (a_m == 0)) begin
 281           z[31] <= b_s;
 282           z[30:23] <= b_e[7:0] + 127;
 283           z[22:0] <= b_m[26:3];
 284           state <= put_z;
 285         //if b is zero return a
 286         end else if (($signed(b_e) == -127) && (b_m == 0)) begin
 287           z[31] <= a_s;
 288           z[30:23] <= a_e[7:0] + 127;
 289           z[22:0] <= a_m[26:3];
 290           state <= put_z;
 291         end else begin
 292           //Denormalised Number
 293           if ($signed(a_e) == -127) begin
 294             a_e <= -126;
 295           end else begin
 296             a_m[26] <= 1;
 297           end
 298           //Denormalised Number
 299           if ($signed(b_e) == -127) begin
 300             b_e <= -126;
 301           end else begin
 302             b_m[26] <= 1;
 303           end
 304           state <= align;
 305         end
 306       end
 307
 308       align:
 309       begin
 310         if ($signed(a_e) > $signed(b_e)) begin
 311           b_e <= b_e + 1;
 312           b_m <= b_m >> 1;
 313           b_m[0] <= b_m[0] | b_m[1];
 314         end else if ($signed(a_e) < $signed(b_e)) begin
 315           a_e <= a_e + 1;
 316           a_m <= a_m >> 1;
 317           a_m[0] <= a_m[0] | a_m[1];
 318         end else begin
 319           state <= add_0;
 320         end
 321       end
 322
 323       add_0:
 324       begin
 325         z_e <= a_e;
 326         if (a_s == b_s) begin
 327           tot <= a_m + b_m;
 328           z_s <= a_s;
 329         end else begin
 330           if (a_m >= b_m) begin
 331             tot <= a_m - b_m;
 332             z_s <= a_s;
 333           end else begin
 334             tot <= b_m - a_m;
 335             z_s <= b_s;
 336           end
 337         end
 338         state <= add_1;
 339       end
 340
 341       add_1:
 342       begin
 343         if (tot[27]) begin
 344           z_m <= tot[27:4];
 345           guard <= tot[3];
 346           round_bit <= tot[2];
 347           sticky <= tot[1] | tot[0];
 348           z_e <= z_e + 1;
 349         end else begin
 350           z_m <= tot[26:3];
 351           guard <= tot[2];
 352           round_bit <= tot[1];
 353           sticky <= tot[0];
 354         end
 355         state <= normalise_1;
 356       end
 357
 358       normalise_1:
 359       begin
 360         if (z_m[23] == 0 && $signed(z_e) > -126) begin
 361           z_e <= z_e - 1;
 362           z_m <= z_m << 1;
 363           z_m[0] <= guard;
 364           guard <= round_bit;
 365           round_bit <= 0;
 366         end else begin
 367           state <= normalise_2;
 368         end
 369       end
 370
 371       normalise_2:
 372       begin
 373         if ($signed(z_e) < -126) begin
 374           z_e <= z_e + 1;
 375           z_m <= z_m >> 1;
 376           guard <= z_m[0];
 377           round_bit <= guard;
 378           sticky <= sticky | round_bit;
 379         end else begin
 380           state <= round;
 381         end
 382       end
 383
 384       round:
 385       begin
 386         if (guard && (round_bit | sticky | z_m[0])) begin
 387           z_m <= z_m + 1;
 388           if (z_m == 24'hffffff) begin
 389             z_e <=z_e + 1;
 390           end
 391         end
 392         state <= pack;
 393       end
 394
 395       pack:
 396       begin
 397         z[22 : 0] <= z_m[22:0];
 398         z[30 : 23] <= z_e[7:0] + 127;
 399         z[31] <= z_s;
 400         if ($signed(z_e) == -126 && z_m[23] == 0) begin
 401           z[30 : 23] <= 0;
 402         end
 403         if ($signed(z_e) == -126 && z_m[23:0] == 24'h0) begin
 404           z[31] <= 1'b0; // FIX SIGN BUG: -a + a = +0.
 405         end
 406         //if overflow occurs, return inf
 407         if ($signed(z_e) > 127) begin
 408           z[22 : 0] <= 0;
 409           z[30 : 23] <= 255;
 410           z[31] <= z_s;
 411         end
 412         state <= put_z;
 413       end
 414
 415       put_z:
 416       begin
 417         s_out_z_stb <= 1;
 418         s_out_z <= z;
 419         if (s_out_z_stb && out_z_ack) begin
 420           s_out_z_stb <= 0;
 421           state <= get_a;
 422         end
 423       end
 424
 425     endcase
 426
 427     if (rst == 1) begin
 428       state <= get_a;
 429       s_in_a_ack <= 0;
 430       s_in_b_ack <= 0;
 431       s_out_z_stb <= 0;
 432     end
 433
 434   end
 435   assign in_a_ack = s_in_a_ack;
 436   assign in_b_ack = s_in_b_ack;
 437   assign out_z_stb = s_out_z_stb;
 438   assign out_z = s_out_z;
 439
 440 endmodule
 441 """
 442
 443 if __name__ == "__main__":
 444     alu = FPADD(width=32)
 445     main(alu, ports=[
 446                     alu.in_a, alu.in_a_stb, alu.in_a_ack,
 447                     alu.in_b, alu.in_b_stb, alu.in_b_ack,
 448                     alu.out_z, alu.out_z_stb, alu.out_z_ack,
 449         ])