src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8
   9 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  10 from fpbase import MultiShiftRMerge
  11 #from fpbase import FPNumShiftMultiRight
  12
  13 class FPState(FPBase):
  14     def __init__(self, state_from):
  15         self.state_from = state_from
  16
  17     def set_inputs(self, inputs):
  18         self.inputs = inputs
  19         for k,v in inputs.items():
  20             setattr(self, k, v)
  21
  22     def set_outputs(self, outputs):
  23         self.outputs = outputs
  24         for k,v in outputs.items():
  25             setattr(self, k, v)
  26
  27
  28 class FPGetOpMod:
  29     def __init__(self, width):
  30         self.in_op = FPOp(width)
  31         self.out_op = FPNumIn(self.in_op, width)
  32         self.out_decode = Signal(reset_less=True)
  33
  34     def elaborate(self, platform):
  35         m = Module()
  36         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  37         #m.submodules.get_op_in = self.in_op
  38         m.submodules.get_op_out = self.out_op
  39         with m.If(self.out_decode):
  40             m.d.comb += [
  41                 self.out_op.decode(self.in_op.v),
  42             ]
  43         return m
  44
  45
  46 class FPGetOp(FPState):
  47     """ gets operand
  48     """
  49
  50     def __init__(self, in_state, out_state, in_op, width):
  51         FPState.__init__(self, in_state)
  52         self.out_state = out_state
  53         self.mod = FPGetOpMod(width)
  54         self.in_op = in_op
  55         self.out_op = FPNumIn(in_op, width)
  56         self.out_decode = Signal(reset_less=True)
  57
  58     def setup(self, m, in_op):
  59         """ links module to inputs and outputs
  60         """
  61         setattr(m.submodules, self.state_from, self.mod)
  62         m.d.comb += self.mod.in_op.copy(in_op)
  63         m.d.comb += self.out_op.v.eq(self.mod.out_op.v)
  64         m.d.comb += self.out_decode.eq(self.mod.out_decode)
  65
  66     def action(self, m):
  67         with m.If(self.out_decode):
  68             m.next = self.out_state
  69             m.d.sync += [
  70                 self.in_op.ack.eq(0),
  71                 self.out_op.copy(self.mod.out_op)
  72             ]
  73         with m.Else():
  74             m.d.sync += self.in_op.ack.eq(1)
  75
  76
  77 class FPAddSpecialCasesMod:
  78     """ special cases: NaNs, infs, zeros, denormalised
  79         NOTE: some of these are unique to add.  see "Special Operations"
  80         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  81     """
  82
  83     def __init__(self, width):
  84         self.in_a = FPNumBase(width)
  85         self.in_b = FPNumBase(width)
  86         self.out_z = FPNumOut(width, False)
  87         self.out_do_z = Signal(reset_less=True)
  88
  89     def elaborate(self, platform):
  90         m = Module()
  91
  92         m.submodules.sc_in_a = self.in_a
  93         m.submodules.sc_in_b = self.in_b
  94         m.submodules.sc_out_z = self.out_z
  95
  96         s_nomatch = Signal()
  97         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
  98
  99         m_match = Signal()
 100         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 101
 102         # if a is NaN or b is NaN return NaN
 103         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 104             m.d.comb += self.out_do_z.eq(1)
 105             m.d.comb += self.out_z.nan(0)
 106
 107         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 108         # under review
 109
 110         ## if a is zero and b is NaN return -b
 111         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 112         #    m.d.comb += self.out_do_z.eq(1)
 113         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 114
 115         ## if b is zero and a is NaN return -a
 116         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 117         #    m.d.comb += self.out_do_z.eq(1)
 118         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 119
 120         ## if a is -zero and b is NaN return -b
 121         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 122         #    m.d.comb += self.out_do_z.eq(1)
 123         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 124
 125         ## if b is -zero and a is NaN return -a
 126         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 127         #    m.d.comb += self.out_do_z.eq(1)
 128         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 129
 130         # if a is inf return inf (or NaN)
 131         with m.Elif(self.in_a.is_inf):
 132             m.d.comb += self.out_do_z.eq(1)
 133             m.d.comb += self.out_z.inf(self.in_a.s)
 134             # if a is inf and signs don't match return NaN
 135             with m.If(self.in_b.exp_128 & s_nomatch):
 136                 m.d.comb += self.out_z.nan(0)
 137
 138         # if b is inf return inf
 139         with m.Elif(self.in_b.is_inf):
 140             m.d.comb += self.out_do_z.eq(1)
 141             m.d.comb += self.out_z.inf(self.in_b.s)
 142
 143         # if a is zero and b zero return signed-a/b
 144         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 145             m.d.comb += self.out_do_z.eq(1)
 146             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 147                                           self.in_b.e,
 148                                           self.in_b.m[3:-1])
 149
 150         # if a is zero return b
 151         with m.Elif(self.in_a.is_zero):
 152             m.d.comb += self.out_do_z.eq(1)
 153             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 154                                       self.in_b.m[3:-1])
 155
 156         # if b is zero return a
 157         with m.Elif(self.in_b.is_zero):
 158             m.d.comb += self.out_do_z.eq(1)
 159             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 160                                       self.in_a.m[3:-1])
 161
 162         # if a equal to -b return zero (+ve zero)
 163         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 164             m.d.comb += self.out_do_z.eq(1)
 165             m.d.comb += self.out_z.zero(0)
 166
 167         # Denormalised Number checks
 168         with m.Else():
 169             m.d.comb += self.out_do_z.eq(0)
 170
 171         return m
 172
 173
 174 class FPID:
 175     def __init__(self, id_wid):
 176         self.id_wid = id_wid
 177         if self.id_wid:
 178             self.in_mid = Signal(width, reset_less)
 179             self.out_mid = Signal(width, reset_less)
 180         else:
 181             self.in_mid = None
 182             self.out_mid = None
 183
 184     def idsync(self, m):
 185         if self.id_wid:
 186             m.d.sync += self.out_mid.eq(self.in_mid)
 187
 188
 189 class FPAddSpecialCases(FPState, FPID):
 190     """ special cases: NaNs, infs, zeros, denormalised
 191         NOTE: some of these are unique to add.  see "Special Operations"
 192         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 193     """
 194
 195     def __init__(self, width, id_wid):
 196         FPState.__init__(self, "special_cases")
 197         FPID.__init__(self, id_wid)
 198         self.mod = FPAddSpecialCasesMod(width)
 199         self.out_z = FPNumOut(width, False)
 200         self.out_do_z = Signal(reset_less=True)
 201
 202     def setup(self, m, in_a, in_b, in_mid):
 203         """ links module to inputs and outputs
 204         """
 205         m.submodules.specialcases = self.mod
 206         m.d.comb += self.mod.in_a.copy(in_a)
 207         m.d.comb += self.mod.in_b.copy(in_b)
 208         #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
 209         m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
 210         if self.in_mid:
 211             m.d.comb += self.in_mid.eq(in_mid)
 212
 213     def action(self, m):
 214         self.idsync(m)
 215         with m.If(self.out_do_z):
 216             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 217             m.next = "put_z"
 218         with m.Else():
 219             m.next = "denormalise"
 220
 221
 222 class FPAddDeNormMod(FPState):
 223
 224     def __init__(self, width):
 225         self.in_a = FPNumBase(width)
 226         self.in_b = FPNumBase(width)
 227         self.out_a = FPNumBase(width)
 228         self.out_b = FPNumBase(width)
 229
 230     def elaborate(self, platform):
 231         m = Module()
 232         m.submodules.denorm_in_a = self.in_a
 233         m.submodules.denorm_in_b = self.in_b
 234         m.submodules.denorm_out_a = self.out_a
 235         m.submodules.denorm_out_b = self.out_b
 236         # hmmm, don't like repeating identical code
 237         m.d.comb += self.out_a.copy(self.in_a)
 238         with m.If(self.in_a.exp_n127):
 239             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 240         with m.Else():
 241             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 242
 243         m.d.comb += self.out_b.copy(self.in_b)
 244         with m.If(self.in_b.exp_n127):
 245             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 246         with m.Else():
 247             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 248
 249         return m
 250
 251
 252 class FPAddDeNorm(FPState, FPID):
 253
 254     def __init__(self, width, id_wid):
 255         FPState.__init__(self, "denormalise")
 256         FPID.__init__(self, id_wid)
 257         self.mod = FPAddDeNormMod(width)
 258         self.out_a = FPNumBase(width)
 259         self.out_b = FPNumBase(width)
 260
 261     def setup(self, m, in_a, in_b, in_mid):
 262         """ links module to inputs and outputs
 263         """
 264         m.submodules.denormalise = self.mod
 265         m.d.comb += self.mod.in_a.copy(in_a)
 266         m.d.comb += self.mod.in_b.copy(in_b)
 267         if self.in_mid:
 268             m.d.comb += self.in_mid.eq(in_mid)
 269
 270     def action(self, m):
 271         self.idsync(m)
 272         # Denormalised Number checks
 273         m.next = "align"
 274         m.d.sync += self.out_a.copy(self.mod.out_a)
 275         m.d.sync += self.out_b.copy(self.mod.out_b)
 276
 277
 278 class FPAddAlignMultiMod(FPState):
 279
 280     def __init__(self, width):
 281         self.in_a = FPNumBase(width)
 282         self.in_b = FPNumBase(width)
 283         self.out_a = FPNumIn(None, width)
 284         self.out_b = FPNumIn(None, width)
 285         self.exp_eq = Signal(reset_less=True)
 286
 287     def elaborate(self, platform):
 288         # This one however (single-cycle) will do the shift
 289         # in one go.
 290
 291         m = Module()
 292
 293         m.submodules.align_in_a = self.in_a
 294         m.submodules.align_in_b = self.in_b
 295         m.submodules.align_out_a = self.out_a
 296         m.submodules.align_out_b = self.out_b
 297
 298         # NOTE: this does *not* do single-cycle multi-shifting,
 299         #       it *STAYS* in the align state until exponents match
 300
 301         # exponent of a greater than b: shift b down
 302         m.d.comb += self.exp_eq.eq(0)
 303         m.d.comb += self.out_a.copy(self.in_a)
 304         m.d.comb += self.out_b.copy(self.in_b)
 305         agtb = Signal(reset_less=True)
 306         altb = Signal(reset_less=True)
 307         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 308         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 309         with m.If(agtb):
 310             m.d.comb += self.out_b.shift_down(self.in_b)
 311         # exponent of b greater than a: shift a down
 312         with m.Elif(altb):
 313             m.d.comb += self.out_a.shift_down(self.in_a)
 314         # exponents equal: move to next stage.
 315         with m.Else():
 316             m.d.comb += self.exp_eq.eq(1)
 317         return m
 318
 319
 320 class FPAddAlignMulti(FPState, FPID):
 321
 322     def __init__(self, width, id_wid):
 323         FPID.__init__(self, id_wid)
 324         FPState.__init__(self, "align")
 325         self.mod = FPAddAlignMultiMod(width)
 326         self.out_a = FPNumIn(None, width)
 327         self.out_b = FPNumIn(None, width)
 328         self.exp_eq = Signal(reset_less=True)
 329
 330     def setup(self, m, in_a, in_b, in_mid):
 331         """ links module to inputs and outputs
 332         """
 333         m.submodules.align = self.mod
 334         m.d.comb += self.mod.in_a.copy(in_a)
 335         m.d.comb += self.mod.in_b.copy(in_b)
 336         #m.d.comb += self.out_a.copy(self.mod.out_a)
 337         #m.d.comb += self.out_b.copy(self.mod.out_b)
 338         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 339         if self.in_mid:
 340             m.d.comb += self.in_mid.eq(in_mid)
 341
 342     def action(self, m):
 343         self.idsync(m)
 344         m.d.sync += self.out_a.copy(self.mod.out_a)
 345         m.d.sync += self.out_b.copy(self.mod.out_b)
 346         with m.If(self.exp_eq):
 347             m.next = "add_0"
 348
 349
 350 class FPAddAlignSingleMod:
 351
 352     def __init__(self, width):
 353         self.width = width
 354         self.in_a = FPNumBase(width)
 355         self.in_b = FPNumBase(width)
 356         self.out_a = FPNumIn(None, width)
 357         self.out_b = FPNumIn(None, width)
 358
 359     def elaborate(self, platform):
 360         """ Aligns A against B or B against A, depending on which has the
 361             greater exponent.  This is done in a *single* cycle using
 362             variable-width bit-shift
 363
 364             the shifter used here is quite expensive in terms of gates.
 365             Mux A or B in (and out) into temporaries, as only one of them
 366             needs to be aligned against the other
 367         """
 368         m = Module()
 369
 370         m.submodules.align_in_a = self.in_a
 371         m.submodules.align_in_b = self.in_b
 372         m.submodules.align_out_a = self.out_a
 373         m.submodules.align_out_b = self.out_b
 374
 375         # temporary (muxed) input and output to be shifted
 376         t_inp = FPNumBase(self.width)
 377         t_out = FPNumIn(None, self.width)
 378         espec = (len(self.in_a.e), True)
 379         msr = MultiShiftRMerge(self.in_a.m_width, espec)
 380         m.submodules.align_t_in = t_inp
 381         m.submodules.align_t_out = t_out
 382         m.submodules.multishift_r = msr
 383
 384         ediff = Signal(espec, reset_less=True)
 385         ediffr = Signal(espec, reset_less=True)
 386         tdiff = Signal(espec, reset_less=True)
 387         elz = Signal(reset_less=True)
 388         egz = Signal(reset_less=True)
 389
 390         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 391         m.d.comb += msr.inp.eq(t_inp.m)
 392         m.d.comb += msr.diff.eq(tdiff)
 393         m.d.comb += t_out.m.eq(msr.m)
 394         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 395         m.d.comb += t_out.s.eq(t_inp.s)
 396
 397         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 398         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 399         m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
 400         m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
 401
 402         # default: A-exp == B-exp, A and B untouched (fall through)
 403         m.d.comb += self.out_a.copy(self.in_a)
 404         m.d.comb += self.out_b.copy(self.in_b)
 405         # only one shifter (muxed)
 406         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 407         # exponent of a greater than b: shift b down
 408         with m.If(egz):
 409             m.d.comb += [t_inp.copy(self.in_b),
 410                          tdiff.eq(ediff),
 411                          self.out_b.copy(t_out),
 412                          self.out_b.s.eq(self.in_b.s), # whoops forgot sign
 413                         ]
 414         # exponent of b greater than a: shift a down
 415         with m.Elif(elz):
 416             m.d.comb += [t_inp.copy(self.in_a),
 417                          tdiff.eq(ediffr),
 418                          self.out_a.copy(t_out),
 419                          self.out_a.s.eq(self.in_a.s), # whoops forgot sign
 420                         ]
 421         return m
 422
 423
 424 class FPAddAlignSingle(FPState, FPID):
 425
 426     def __init__(self, width, id_wid):
 427         FPState.__init__(self, "align")
 428         FPID.__init__(self, id_wid)
 429         self.mod = FPAddAlignSingleMod(width)
 430         self.out_a = FPNumIn(None, width)
 431         self.out_b = FPNumIn(None, width)
 432
 433     def setup(self, m, in_a, in_b, in_mid):
 434         """ links module to inputs and outputs
 435         """
 436         m.submodules.align = self.mod
 437         m.d.comb += self.mod.in_a.copy(in_a)
 438         m.d.comb += self.mod.in_b.copy(in_b)
 439         if self.in_mid:
 440             m.d.comb += self.in_mid.eq(in_mid)
 441
 442     def action(self, m):
 443         self.idsync(m)
 444         # NOTE: could be done as comb
 445         m.d.sync += self.out_a.copy(self.mod.out_a)
 446         m.d.sync += self.out_b.copy(self.mod.out_b)
 447         m.next = "add_0"
 448
 449
 450 class FPAddStage0Mod:
 451
 452     def __init__(self, width):
 453         self.in_a = FPNumBase(width)
 454         self.in_b = FPNumBase(width)
 455         self.in_z = FPNumBase(width, False)
 456         self.out_z = FPNumBase(width, False)
 457         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 458
 459     def elaborate(self, platform):
 460         m = Module()
 461         m.submodules.add0_in_a = self.in_a
 462         m.submodules.add0_in_b = self.in_b
 463         m.submodules.add0_out_z = self.out_z
 464
 465         m.d.comb += self.out_z.e.eq(self.in_a.e)
 466
 467         # store intermediate tests (and zero-extended mantissas)
 468         seq = Signal(reset_less=True)
 469         mge = Signal(reset_less=True)
 470         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
 471         bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
 472         m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
 473                      mge.eq(self.in_a.m >= self.in_b.m),
 474                      am0.eq(Cat(self.in_a.m, 0)),
 475                      bm0.eq(Cat(self.in_b.m, 0))
 476                     ]
 477         # same-sign (both negative or both positive) add mantissas
 478         with m.If(seq):
 479             m.d.comb += [
 480                 self.out_tot.eq(am0 + bm0),
 481                 self.out_z.s.eq(self.in_a.s)
 482             ]
 483         # a mantissa greater than b, use a
 484         with m.Elif(mge):
 485             m.d.comb += [
 486                 self.out_tot.eq(am0 - bm0),
 487                 self.out_z.s.eq(self.in_a.s)
 488             ]
 489         # b mantissa greater than a, use b
 490         with m.Else():
 491             m.d.comb += [
 492                 self.out_tot.eq(bm0 - am0),
 493                 self.out_z.s.eq(self.in_b.s)
 494         ]
 495         return m
 496
 497
 498 class FPAddStage0(FPState):
 499     """ First stage of add.  covers same-sign (add) and subtract
 500         special-casing when mantissas are greater or equal, to
 501         give greatest accuracy.
 502     """
 503
 504     def __init__(self, width):
 505         FPState.__init__(self, "add_0")
 506         self.mod = FPAddStage0Mod(width)
 507         self.out_z = FPNumBase(width, False)
 508         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 509
 510     def setup(self, m, in_a, in_b):
 511         """ links module to inputs and outputs
 512         """
 513         m.submodules.add0 = self.mod
 514
 515         m.d.comb += self.mod.in_a.copy(in_a)
 516         m.d.comb += self.mod.in_b.copy(in_b)
 517
 518     def action(self, m):
 519         m.next = "add_1"
 520         # NOTE: these could be done as combinatorial (merge add0+add1)
 521         m.d.sync += self.out_z.copy(self.mod.out_z)
 522         m.d.sync += self.out_tot.eq(self.mod.out_tot)
 523
 524
 525 class FPAddStage1Mod(FPState):
 526     """ Second stage of add: preparation for normalisation.
 527         detects when tot sum is too big (tot[27] is kinda a carry bit)
 528     """
 529
 530     def __init__(self, width):
 531         self.out_norm = Signal(reset_less=True)
 532         self.in_z = FPNumBase(width, False)
 533         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 534         self.out_z = FPNumBase(width, False)
 535         self.out_of = Overflow()
 536
 537     def elaborate(self, platform):
 538         m = Module()
 539         #m.submodules.norm1_in_overflow = self.in_of
 540         #m.submodules.norm1_out_overflow = self.out_of
 541         #m.submodules.norm1_in_z = self.in_z
 542         #m.submodules.norm1_out_z = self.out_z
 543         m.d.comb += self.out_z.copy(self.in_z)
 544         # tot[27] gets set when the sum overflows. shift result down
 545         with m.If(self.in_tot[-1]):
 546             m.d.comb += [
 547                 self.out_z.m.eq(self.in_tot[4:]),
 548                 self.out_of.m0.eq(self.in_tot[4]),
 549                 self.out_of.guard.eq(self.in_tot[3]),
 550                 self.out_of.round_bit.eq(self.in_tot[2]),
 551                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 552                 self.out_z.e.eq(self.in_z.e + 1)
 553         ]
 554         # tot[27] zero case
 555         with m.Else():
 556             m.d.comb += [
 557                 self.out_z.m.eq(self.in_tot[3:]),
 558                 self.out_of.m0.eq(self.in_tot[3]),
 559                 self.out_of.guard.eq(self.in_tot[2]),
 560                 self.out_of.round_bit.eq(self.in_tot[1]),
 561                 self.out_of.sticky.eq(self.in_tot[0])
 562         ]
 563         return m
 564
 565
 566 class FPAddStage1(FPState):
 567
 568     def __init__(self, width):
 569         FPState.__init__(self, "add_1")
 570         self.mod = FPAddStage1Mod(width)
 571         self.out_z = FPNumBase(width, False)
 572         self.out_of = Overflow()
 573         self.norm_stb = Signal()
 574
 575     def setup(self, m, in_tot, in_z):
 576         """ links module to inputs and outputs
 577         """
 578         m.submodules.add1 = self.mod
 579
 580         m.d.comb += self.mod.in_z.copy(in_z)
 581         m.d.comb += self.mod.in_tot.eq(in_tot)
 582
 583         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 584
 585     def action(self, m):
 586         m.submodules.add1_out_overflow = self.out_of
 587         m.d.sync += self.out_of.copy(self.mod.out_of)
 588         m.d.sync += self.out_z.copy(self.mod.out_z)
 589         m.d.sync += self.norm_stb.eq(1)
 590         m.next = "normalise_1"
 591
 592
 593 class FPNorm1ModSingle:
 594
 595     def __init__(self, width):
 596         self.width = width
 597         self.in_select = Signal(reset_less=True)
 598         self.out_norm = Signal(reset_less=True)
 599         self.in_z = FPNumBase(width, False)
 600         self.in_of = Overflow()
 601         self.temp_z = FPNumBase(width, False)
 602         self.temp_of = Overflow()
 603         self.out_z = FPNumBase(width, False)
 604         self.out_of = Overflow()
 605
 606     def elaborate(self, platform):
 607         m = Module()
 608
 609         mwid = self.out_z.m_width+2
 610         pe = PriorityEncoder(mwid)
 611         m.submodules.norm_pe = pe
 612
 613         m.submodules.norm1_out_z = self.out_z
 614         m.submodules.norm1_out_overflow = self.out_of
 615         m.submodules.norm1_temp_z = self.temp_z
 616         m.submodules.norm1_temp_of = self.temp_of
 617         m.submodules.norm1_in_z = self.in_z
 618         m.submodules.norm1_in_overflow = self.in_of
 619
 620         in_z = FPNumBase(self.width, False)
 621         in_of = Overflow()
 622         m.submodules.norm1_insel_z = in_z
 623         m.submodules.norm1_insel_overflow = in_of
 624
 625         espec = (len(in_z.e), True)
 626         ediff_n126 = Signal(espec, reset_less=True)
 627         msr = MultiShiftRMerge(mwid, espec)
 628         m.submodules.multishift_r = msr
 629
 630         # select which of temp or in z/of to use
 631         with m.If(self.in_select):
 632             m.d.comb += in_z.copy(self.in_z)
 633             m.d.comb += in_of.copy(self.in_of)
 634         with m.Else():
 635             m.d.comb += in_z.copy(self.temp_z)
 636             m.d.comb += in_of.copy(self.temp_of)
 637         # initialise out from in (overridden below)
 638         m.d.comb += self.out_z.copy(in_z)
 639         m.d.comb += self.out_of.copy(in_of)
 640         # normalisation increase/decrease conditions
 641         decrease = Signal(reset_less=True)
 642         increase = Signal(reset_less=True)
 643         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 644         m.d.comb += increase.eq(in_z.exp_lt_n126)
 645         m.d.comb += self.out_norm.eq(0) # loop-end condition
 646         # decrease exponent
 647         with m.If(decrease):
 648             # *sigh* not entirely obvious: count leading zeros (clz)
 649             # with a PriorityEncoder: to find from the MSB
 650             # we reverse the order of the bits.
 651             temp_m = Signal(mwid, reset_less=True)
 652             temp_s = Signal(mwid+1, reset_less=True)
 653             clz = Signal((len(in_z.e), True), reset_less=True)
 654             # make sure that the amount to decrease by does NOT
 655             # go below the minimum non-INF/NaN exponent
 656             limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
 657                          in_z.exp_sub_n126)
 658             m.d.comb += [
 659                 # cat round and guard bits back into the mantissa
 660                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 661                 pe.i.eq(temp_m[::-1]),          # inverted
 662                 clz.eq(limclz),                 # count zeros from MSB down
 663                 temp_s.eq(temp_m << clz),       # shift mantissa UP
 664                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
 665                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
 666                 self.out_of.m0.eq(temp_s[2]),   # copy of mantissa[0]
 667                 # overflow in bits 0..1: got shifted too (leave sticky)
 668                 self.out_of.guard.eq(temp_s[1]),     # guard
 669                 self.out_of.round_bit.eq(temp_s[0]), # round
 670             ]
 671         # increase exponent
 672         with m.Elif(increase):
 673             temp_m = Signal(mwid+1, reset_less=True)
 674             m.d.comb += [
 675                 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
 676                               in_z.m)),
 677                 ediff_n126.eq(in_z.N126 - in_z.e),
 678                 # connect multi-shifter to inp/out mantissa (and ediff)
 679                 msr.inp.eq(temp_m),
 680                 msr.diff.eq(ediff_n126),
 681                 self.out_z.m.eq(msr.m[3:]),
 682                 self.out_of.m0.eq(temp_s[3]),   # copy of mantissa[0]
 683                 # overflow in bits 0..1: got shifted too (leave sticky)
 684                 self.out_of.guard.eq(temp_s[2]),     # guard
 685                 self.out_of.round_bit.eq(temp_s[1]), # round
 686                 self.out_of.sticky.eq(temp_s[0]), # sticky
 687                 self.out_z.e.eq(in_z.e + ediff_n126),
 688             ]
 689
 690         return m
 691
 692
 693 class FPNorm1ModMulti:
 694
 695     def __init__(self, width, single_cycle=True):
 696         self.width = width
 697         self.in_select = Signal(reset_less=True)
 698         self.out_norm = Signal(reset_less=True)
 699         self.in_z = FPNumBase(width, False)
 700         self.in_of = Overflow()
 701         self.temp_z = FPNumBase(width, False)
 702         self.temp_of = Overflow()
 703         self.out_z = FPNumBase(width, False)
 704         self.out_of = Overflow()
 705
 706     def elaborate(self, platform):
 707         m = Module()
 708
 709         m.submodules.norm1_out_z = self.out_z
 710         m.submodules.norm1_out_overflow = self.out_of
 711         m.submodules.norm1_temp_z = self.temp_z
 712         m.submodules.norm1_temp_of = self.temp_of
 713         m.submodules.norm1_in_z = self.in_z
 714         m.submodules.norm1_in_overflow = self.in_of
 715
 716         in_z = FPNumBase(self.width, False)
 717         in_of = Overflow()
 718         m.submodules.norm1_insel_z = in_z
 719         m.submodules.norm1_insel_overflow = in_of
 720
 721         # select which of temp or in z/of to use
 722         with m.If(self.in_select):
 723             m.d.comb += in_z.copy(self.in_z)
 724             m.d.comb += in_of.copy(self.in_of)
 725         with m.Else():
 726             m.d.comb += in_z.copy(self.temp_z)
 727             m.d.comb += in_of.copy(self.temp_of)
 728         # initialise out from in (overridden below)
 729         m.d.comb += self.out_z.copy(in_z)
 730         m.d.comb += self.out_of.copy(in_of)
 731         # normalisation increase/decrease conditions
 732         decrease = Signal(reset_less=True)
 733         increase = Signal(reset_less=True)
 734         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 735         m.d.comb += increase.eq(in_z.exp_lt_n126)
 736         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
 737         # decrease exponent
 738         with m.If(decrease):
 739             m.d.comb += [
 740                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
 741                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
 742                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
 743                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
 744                 self.out_of.round_bit.eq(0),        # reset round bit
 745                 self.out_of.m0.eq(in_of.guard),
 746             ]
 747         # increase exponent
 748         with m.Elif(increase):
 749             m.d.comb += [
 750                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
 751                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
 752                 self.out_of.guard.eq(in_z.m[0]),
 753                 self.out_of.m0.eq(in_z.m[1]),
 754                 self.out_of.round_bit.eq(in_of.guard),
 755                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
 756             ]
 757
 758         return m
 759
 760
 761 class FPNorm1(FPState):
 762
 763     def __init__(self, width, single_cycle=True):
 764         FPState.__init__(self, "normalise_1")
 765         if single_cycle:
 766             self.mod = FPNorm1ModSingle(width)
 767         else:
 768             self.mod = FPNorm1ModMulti(width)
 769         self.stb = Signal(reset_less=True)
 770         self.ack = Signal(reset=0, reset_less=True)
 771         self.out_norm = Signal(reset_less=True)
 772         self.in_accept = Signal(reset_less=True)
 773         self.temp_z = FPNumBase(width)
 774         self.temp_of = Overflow()
 775         self.out_z = FPNumBase(width)
 776         self.out_roundz = Signal(reset_less=True)
 777
 778     def setup(self, m, in_z, in_of, norm_stb):
 779         """ links module to inputs and outputs
 780         """
 781         m.submodules.normalise_1 = self.mod
 782
 783         m.d.comb += self.mod.in_z.copy(in_z)
 784         m.d.comb += self.mod.in_of.copy(in_of)
 785
 786         m.d.comb += self.mod.in_select.eq(self.in_accept)
 787         m.d.comb += self.mod.temp_z.copy(self.temp_z)
 788         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 789
 790         m.d.comb += self.out_z.copy(self.mod.out_z)
 791         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 792
 793         m.d.comb += self.stb.eq(norm_stb)
 794         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 795
 796     def action(self, m):
 797
 798         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
 799         m.d.sync += self.temp_of.copy(self.mod.out_of)
 800         m.d.sync += self.temp_z.copy(self.out_z)
 801         with m.If(self.out_norm):
 802             with m.If(self.in_accept):
 803                 m.d.sync += [
 804                     self.ack.eq(1),
 805                 ]
 806             with m.Else():
 807                 m.d.sync += self.ack.eq(0)
 808         with m.Else():
 809             # normalisation not required (or done).
 810             m.next = "round"
 811             m.d.sync += self.ack.eq(1)
 812             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 813
 814
 815 class FPRoundMod:
 816
 817     def __init__(self, width):
 818         self.in_roundz = Signal(reset_less=True)
 819         self.in_z = FPNumBase(width, False)
 820         self.out_z = FPNumBase(width, False)
 821
 822     def elaborate(self, platform):
 823         m = Module()
 824         m.d.comb += self.out_z.copy(self.in_z)
 825         with m.If(self.in_roundz):
 826             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 827             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 828                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 829         return m
 830
 831
 832 class FPRound(FPState):
 833
 834     def __init__(self, width):
 835         FPState.__init__(self, "round")
 836         self.mod = FPRoundMod(width)
 837         self.out_z = FPNumBase(width)
 838
 839     def setup(self, m, in_z, roundz):
 840         """ links module to inputs and outputs
 841         """
 842         m.submodules.roundz = self.mod
 843
 844         m.d.comb += self.mod.in_z.copy(in_z)
 845         m.d.comb += self.mod.in_roundz.eq(roundz)
 846
 847     def action(self, m):
 848         m.d.sync += self.out_z.copy(self.mod.out_z)
 849         m.next = "corrections"
 850
 851
 852 class FPCorrectionsMod:
 853
 854     def __init__(self, width):
 855         self.in_z = FPNumOut(width, False)
 856         self.out_z = FPNumOut(width, False)
 857
 858     def elaborate(self, platform):
 859         m = Module()
 860         m.submodules.corr_in_z = self.in_z
 861         m.submodules.corr_out_z = self.out_z
 862         m.d.comb += self.out_z.copy(self.in_z)
 863         with m.If(self.in_z.is_denormalised):
 864             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 865         return m
 866
 867
 868 class FPCorrections(FPState):
 869
 870     def __init__(self, width):
 871         FPState.__init__(self, "corrections")
 872         self.mod = FPCorrectionsMod(width)
 873         self.out_z = FPNumBase(width)
 874
 875     def setup(self, m, in_z):
 876         """ links module to inputs and outputs
 877         """
 878         m.submodules.corrections = self.mod
 879         m.d.comb += self.mod.in_z.copy(in_z)
 880
 881     def action(self, m):
 882         m.d.sync += self.out_z.copy(self.mod.out_z)
 883         m.next = "pack"
 884
 885
 886 class FPPackMod:
 887
 888     def __init__(self, width):
 889         self.in_z = FPNumOut(width, False)
 890         self.out_z = FPNumOut(width, False)
 891
 892     def elaborate(self, platform):
 893         m = Module()
 894         m.submodules.pack_in_z = self.in_z
 895         with m.If(self.in_z.is_overflowed):
 896             m.d.comb += self.out_z.inf(self.in_z.s)
 897         with m.Else():
 898             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 899         return m
 900
 901
 902 class FPPack(FPState):
 903
 904     def __init__(self, width):
 905         FPState.__init__(self, "pack")
 906         self.mod = FPPackMod(width)
 907         self.out_z = FPNumOut(width, False)
 908
 909     def setup(self, m, in_z):
 910         """ links module to inputs and outputs
 911         """
 912         m.submodules.pack = self.mod
 913         m.d.comb += self.mod.in_z.copy(in_z)
 914
 915     def action(self, m):
 916         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
 917         m.next = "pack_put_z"
 918
 919
 920 class FPPutZ(FPState):
 921
 922     def __init__(self, state, in_z, out_z):
 923         FPState.__init__(self, state)
 924         self.in_z = in_z
 925         self.out_z = out_z
 926
 927     def action(self, m):
 928         m.d.sync += [
 929           self.out_z.v.eq(self.in_z.v)
 930         ]
 931         with m.If(self.out_z.stb & self.out_z.ack):
 932             m.d.sync += self.out_z.stb.eq(0)
 933             m.next = "get_a"
 934         with m.Else():
 935             m.d.sync += self.out_z.stb.eq(1)
 936
 937
 938 class FPADD(FPID):
 939
 940     def __init__(self, width, id_wid=None, single_cycle=False):
 941         """ IEEE754 FP Add
 942
 943             * width: bit-width of IEEE754.  supported: 16, 32, 64
 944             * id_wid: an identifier that is sync-connected to the input
 945             * single_cycle: True indicates each stage to complete in 1 clock
 946         """
 947         FPID.__init__(self, id_wid)
 948         self.width = width
 949         self.single_cycle = single_cycle
 950
 951         self.in_a  = FPOp(width)
 952         self.in_b  = FPOp(width)
 953         self.out_z = FPOp(width)
 954
 955         self.states = []
 956
 957     def add_state(self, state):
 958         self.states.append(state)
 959         return state
 960
 961     def get_fragment(self, platform=None):
 962         """ creates the HDL code-fragment for FPAdd
 963         """
 964         m = Module()
 965         m.submodules.in_a = self.in_a
 966         m.submodules.in_b = self.in_b
 967         m.submodules.out_z = self.out_z
 968
 969         geta = self.add_state(FPGetOp("get_a", "get_b",
 970                                       self.in_a, self.width))
 971         geta.setup(m, self.in_a)
 972         a = geta.out_op
 973
 974         getb = self.add_state(FPGetOp("get_b", "special_cases",
 975                                       self.in_b, self.width))
 976         getb.setup(m, self.in_b)
 977         b = getb.out_op
 978
 979         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
 980         sc.setup(m, a, b, self.in_mid)
 981
 982         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
 983         dn.setup(m, a, b, sc.in_mid)
 984
 985         if self.single_cycle:
 986             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
 987             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
 988         else:
 989             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
 990             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
 991
 992         add0 = self.add_state(FPAddStage0(self.width))
 993         add0.setup(m, alm.out_a, alm.out_b)
 994
 995         add1 = self.add_state(FPAddStage1(self.width))
 996         add1.setup(m, add0.out_tot, add0.out_z)
 997
 998         n1 = self.add_state(FPNorm1(self.width))
 999         n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
1000
1001         rn = self.add_state(FPRound(self.width))
1002         rn.setup(m, n1.out_z, n1.out_roundz)
1003
1004         cor = self.add_state(FPCorrections(self.width))
1005         cor.setup(m, rn.out_z)
1006
1007         pa = self.add_state(FPPack(self.width))
1008         pa.setup(m, cor.out_z)
1009
1010         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
1011
1012         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
1013
1014         with m.FSM() as fsm:
1015
1016             for state in self.states:
1017                 with m.State(state.state_from):
1018                     state.action(m)
1019
1020         return m
1021
1022
1023 if __name__ == "__main__":
1024     alu = FPADD(width=32, single_cycle=True)
1025     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
1026
1027
1028     # works... but don't use, just do "python fname.py convert -t v"
1029     #print (verilog.convert(alu, ports=[
1030     #                        ports=alu.in_a.ports() + \
1031     #                              alu.in_b.ports() + \
1032     #                              alu.out_z.ports())