src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main
   7
   8
   9 class FPADD:
  10     def __init__(self, width):
  11         self.width = width
  12
  13         self.in_a     = Signal(width)
  14         self.in_a_stb = Signal()
  15         self.in_a_ack = Signal()
  16
  17         self.in_b     = Signal(width)
  18         self.in_b_stb = Signal()
  19         self.in_b_ack = Signal()
  20
  21         self.out_z     = Signal(width)
  22         self.out_z_stb = Signal()
  23         self.out_z_ack = Signal()
  24
  25         s_out_z_stb  = Signal()
  26         s_out_z      = Signal(width)
  27         s_in_a_ack   = Signal()
  28         s_in_b_ack   = Signal()
  29
  30     def get_fragment(self, platform):
  31         m = Module()
  32
  33         # Latches
  34         a = Signal(self.width)
  35         b = Signal(self.width)
  36         z = Signal(self.width)
  37
  38         # Mantissa
  39         a_m = Signal(27) # ??? seems to be 1 bit extra??
  40         b_m = Signal(27) # ??? seems to be 1 bit extra??
  41         z_m = Signal(24)
  42
  43         # Exponent
  44         a_e = Signal(10)
  45         b_e = Signal(10)
  46         z_e = Signal(10)
  47
  48         # Sign
  49         a_s = Signal()
  50         b_s = Signal()
  51         z_s = Signal()
  52
  53         guard = Signal()
  54         round_bit = Signal()
  55         sticky = Signal()
  56
  57         tot = Signal(28)
  58
  59         with m.FSM() as fsm:
  60
  61             # ******
  62             # gets operand a
  63
  64             with m.State("get_a"):
  65                 with m.If((self.in_a_ack) & (self.in_a_stb)):
  66                     m.next = "get_b"
  67                     m.d.sync += [
  68                         a.eq(self.in_a),
  69                         self.in_a_ack.eq(0)
  70                     ]
  71                 with m.Else():
  72                     m.d.sync += self.in_a_ack.eq(1)
  73
  74             # ******
  75             # gets operand b
  76
  77             with m.State("get_b"):
  78                 with m.If((self.in_b_ack) & (self.in_b_stb)):
  79                     m.next = "get_a"
  80                     m.d.sync += [
  81                         b.eq(self.in_b),
  82                         self.in_b_ack.eq(0)
  83                     ]
  84                 with m.Else():
  85                     m.d.sync += self.in_b_ack.eq(1)
  86
  87             # ******
  88             # unpacks operands into sign, mantissa and exponent
  89
  90             with m.State("unpack"):
  91                 m.next = "special_cases"
  92                 m.d.sync += [
  93                     # mantissa
  94                     a_m.eq(Cat(0, 0, 0, a[0:23])),
  95                     b_m.eq(Cat(0, 0, 0, b[0:23])),
  96                     # exponent (take off exponent bias, here)
  97                     a_e.eq(Cat(a[23:31]) - 127),
  98                     b_e.eq(Cat(b[23:31]) - 127),
  99                     # sign
 100                     a_s.eq(Cat(a[31])),
 101                     b_s.eq(Cat(b[31]))
 102                 ]
 103
 104             # ******
 105             # special cases: NaNs, infs, zeros, denormalised
 106
 107             with m.State("special_cases"):
 108
 109                 # if a is NaN or b is NaN return NaN
 110                 with m.If(((a_e == 128) & (a_m != 0)) | \
 111                           ((b_e == 128) & (b_m != 0))):
 112                     m.next = "put_z"
 113                     m.d.sync += [
 114                           z[31].eq(1),      # sign: 1
 115                           z[23:31].eq(255), # exp: 0b11111...
 116                           z[22].eq(1),      # mantissa top bit: 1
 117                           z[0:22].eq(0)     # mantissa rest: 0b0000...
 118                     ]
 119
 120                 # if a is inf return inf (or NaN)
 121                 with m.Elif(a_e == 128):
 122                     m.next = "put_z"
 123                     m.d.sync += [
 124                         z[31].eq(a_s),    # sign: a_s
 125                         z[23:31].eq(255), # exp: 0b11111...
 126                         z[0:23].eq(0)     # mantissa rest: 0b0000...
 127                     ]
 128                     # if a is inf and signs don't match return NaN
 129                     with m.If((b_e == 128) & (a_s != b_s)):
 130                         m.d.sync += [
 131                           z[31].eq(b_s),    # sign: b_s
 132                           z[23:31].eq(255), # exp: 0b11111...
 133                           z[22].eq(1),      # mantissa top bit: 1
 134                           z[0:22].eq(0)     # mantissa rest: 0b0000...
 135                         ]
 136                 # if b is inf return inf
 137                 with m.Elif(b_e == 128):
 138                     m.next = "put_z"
 139                     m.d.sync += [
 140                         z[31].eq(b_s),    # sign: b_s
 141                         z[23:31].eq(255), # exp: 0b11111...
 142                         z[0:23].eq(0)     # mantissa rest: 0b0000...
 143                     ]
 144
 145                 # if a is zero and b zero return signed-a/b
 146                 with m.Elif(((a_e == -127) & (a_m == 0)) & \
 147                             ((b_e == -127) & (b_m == 0))):
 148                     m.next = "put_z"
 149                     m.d.sync += [
 150                         z[31].eq(a_s & b_s),         # sign: a/b_s
 151                         z[23:31].eq(b_e[0:8] + 127), # exp: b_e (plus bias)
 152                         z[0:23].eq(b_m[3:26])        # mantissa: b_m top bits
 153                     ]
 154
 155                 # if a is zero return b
 156                 with m.Elif((a_e == -127) & (a_m == 0)):
 157                     m.next = "put_z"
 158                     m.d.sync += [
 159                         z[31].eq(b_s),               # sign: a/b_s
 160                         z[23:31].eq(b_e[0:8] + 127), # exp: b_e (plus bias)
 161                         z[0:23].eq(b_m[3:26])        # mantissa: b_m top bits
 162                     ]
 163
 164                 # if b is zero return a
 165                 with m.Elif((b_e == -127) & (b_m == 0)):
 166                     m.next = "put_z"
 167                     m.d.sync += [
 168                         z[31].eq(a_s),               # sign: a/b_s
 169                         z[23:31].eq(a_e[0:8] + 127), # exp: a_e (plus bias)
 170                         z[0:23].eq(a_m[3:26])        # mantissa: a_m top bits
 171                     ]
 172
 173                 # Denormalised Number checks
 174                 with m.Else():
 175                     m.next = "align"
 176                     # denormalise a check
 177                     with m.If(a_e == -127):
 178                         m.d.sync += a_e.eq(-126) # limit a exponent
 179                     with m.Else():
 180                         m.d.sync += a_m[26].eq(1) # set highest mantissa bit
 181                     # denormalise b check
 182                     with m.If(b_e == -127):
 183                         m.d.sync += b_e.eq(-126) # limit b exponent
 184                     with m.Else():
 185                         m.d.sync += b_m[26].eq(1) # set highest mantissa bit
 186         return m
 187
 188 """
 189   always @(posedge clk)
 190   begin
 191
 192     case(state)
 193
 194       get_a:
 195       begin
 196         s_in_a_ack <= 1;
 197         if (s_in_a_ack && in_a_stb) begin
 198           a <= in_a;
 199           s_in_a_ack <= 0;
 200           state <= get_b;
 201         end
 202       end
 203
 204       get_b:
 205       begin
 206         s_in_b_ack <= 1;
 207         if (s_in_b_ack && in_b_stb) begin
 208           b <= in_b;
 209           s_in_b_ack <= 0;
 210           state <= unpack;
 211         end
 212       end
 213
 214       unpack:
 215       begin
 216         a_m <= {a[22 : 0], 3'd0};
 217         b_m <= {b[22 : 0], 3'd0};
 218         a_e <= a[30 : 23] - 127;
 219         b_e <= b[30 : 23] - 127;
 220         a_s <= a[31];
 221         b_s <= b[31];
 222         state <= special_cases;
 223       end
 224
 225       special_cases:
 226       begin
 227         //if a is NaN or b is NaN return NaN
 228         if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
 229           z[31] <= 1;
 230           z[30:23] <= 255;
 231           z[22] <= 1;
 232           z[21:0] <= 0;
 233           state <= put_z;
 234         //if a is inf return inf
 235         end else if (a_e == 128) begin
 236           z[31] <= a_s;
 237           z[30:23] <= 255;
 238           z[22:0] <= 0;
 239           //if a is inf and signs don't match return nan
 240           if ((b_e == 128) && (a_s != b_s)) begin
 241               z[31] <= b_s;
 242               z[30:23] <= 255;
 243               z[22] <= 1;
 244               z[21:0] <= 0;
 245           end
 246           state <= put_z;
 247         //if b is inf return inf
 248         end else if (b_e == 128) begin
 249           z[31] <= b_s;
 250           z[30:23] <= 255;
 251           z[22:0] <= 0;
 252           state <= put_z;
 253         //if a is zero return b
 254         end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
 255           z[31] <= a_s & b_s;
 256           z[30:23] <= b_e[7:0] + 127;
 257           z[22:0] <= b_m[26:3];
 258           state <= put_z;
 259         //if a is zero return b
 260         end else if (($signed(a_e) == -127) && (a_m == 0)) begin
 261           z[31] <= b_s;
 262           z[30:23] <= b_e[7:0] + 127;
 263           z[22:0] <= b_m[26:3];
 264           state <= put_z;
 265         //if b is zero return a
 266         end else if (($signed(b_e) == -127) && (b_m == 0)) begin
 267           z[31] <= a_s;
 268           z[30:23] <= a_e[7:0] + 127;
 269           z[22:0] <= a_m[26:3];
 270           state <= put_z;
 271         end else begin
 272           //Denormalised Number
 273           if ($signed(a_e) == -127) begin
 274             a_e <= -126;
 275           end else begin
 276             a_m[26] <= 1;
 277           end
 278           //Denormalised Number
 279           if ($signed(b_e) == -127) begin
 280             b_e <= -126;
 281           end else begin
 282             b_m[26] <= 1;
 283           end
 284           state <= align;
 285         end
 286       end
 287
 288       align:
 289       begin
 290         if ($signed(a_e) > $signed(b_e)) begin
 291           b_e <= b_e + 1;
 292           b_m <= b_m >> 1;
 293           b_m[0] <= b_m[0] | b_m[1];
 294         end else if ($signed(a_e) < $signed(b_e)) begin
 295           a_e <= a_e + 1;
 296           a_m <= a_m >> 1;
 297           a_m[0] <= a_m[0] | a_m[1];
 298         end else begin
 299           state <= add_0;
 300         end
 301       end
 302
 303       add_0:
 304       begin
 305         z_e <= a_e;
 306         if (a_s == b_s) begin
 307           tot <= a_m + b_m;
 308           z_s <= a_s;
 309         end else begin
 310           if (a_m >= b_m) begin
 311             tot <= a_m - b_m;
 312             z_s <= a_s;
 313           end else begin
 314             tot <= b_m - a_m;
 315             z_s <= b_s;
 316           end
 317         end
 318         state <= add_1;
 319       end
 320
 321       add_1:
 322       begin
 323         if (tot[27]) begin
 324           z_m <= tot[27:4];
 325           guard <= tot[3];
 326           round_bit <= tot[2];
 327           sticky <= tot[1] | tot[0];
 328           z_e <= z_e + 1;
 329         end else begin
 330           z_m <= tot[26:3];
 331           guard <= tot[2];
 332           round_bit <= tot[1];
 333           sticky <= tot[0];
 334         end
 335         state <= normalise_1;
 336       end
 337
 338       normalise_1:
 339       begin
 340         if (z_m[23] == 0 && $signed(z_e) > -126) begin
 341           z_e <= z_e - 1;
 342           z_m <= z_m << 1;
 343           z_m[0] <= guard;
 344           guard <= round_bit;
 345           round_bit <= 0;
 346         end else begin
 347           state <= normalise_2;
 348         end
 349       end
 350
 351       normalise_2:
 352       begin
 353         if ($signed(z_e) < -126) begin
 354           z_e <= z_e + 1;
 355           z_m <= z_m >> 1;
 356           guard <= z_m[0];
 357           round_bit <= guard;
 358           sticky <= sticky | round_bit;
 359         end else begin
 360           state <= round;
 361         end
 362       end
 363
 364       round:
 365       begin
 366         if (guard && (round_bit | sticky | z_m[0])) begin
 367           z_m <= z_m + 1;
 368           if (z_m == 24'hffffff) begin
 369             z_e <=z_e + 1;
 370           end
 371         end
 372         state <= pack;
 373       end
 374
 375       pack:
 376       begin
 377         z[22 : 0] <= z_m[22:0];
 378         z[30 : 23] <= z_e[7:0] + 127;
 379         z[31] <= z_s;
 380         if ($signed(z_e) == -126 && z_m[23] == 0) begin
 381           z[30 : 23] <= 0;
 382         end
 383         if ($signed(z_e) == -126 && z_m[23:0] == 24'h0) begin
 384           z[31] <= 1'b0; // FIX SIGN BUG: -a + a = +0.
 385         end
 386         //if overflow occurs, return inf
 387         if ($signed(z_e) > 127) begin
 388           z[22 : 0] <= 0;
 389           z[30 : 23] <= 255;
 390           z[31] <= z_s;
 391         end
 392         state <= put_z;
 393       end
 394
 395       put_z:
 396       begin
 397         s_out_z_stb <= 1;
 398         s_out_z <= z;
 399         if (s_out_z_stb && out_z_ack) begin
 400           s_out_z_stb <= 0;
 401           state <= get_a;
 402         end
 403       end
 404
 405     endcase
 406
 407     if (rst == 1) begin
 408       state <= get_a;
 409       s_in_a_ack <= 0;
 410       s_in_b_ack <= 0;
 411       s_out_z_stb <= 0;
 412     end
 413
 414   end
 415   assign in_a_ack = s_in_a_ack;
 416   assign in_b_ack = s_in_b_ack;
 417   assign out_z_stb = s_out_z_stb;
 418   assign out_z = s_out_z;
 419
 420 endmodule
 421 """
 422
 423 if __name__ == "__main__":
 424     alu = FPADD(width=32)
 425     main(alu, ports=[
 426                     alu.in_a, alu.in_a_stb, alu.in_a_ack,
 427                     alu.in_b, alu.in_b_stb, alu.in_b_ack,
 428                     alu.out_z, alu.out_z_stb, alu.out_z_ack,
 429         ])