src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 #from fpbase import FPNumShiftMultiRight
  13
  14
  15 class FPState(FPBase):
  16     def __init__(self, state_from):
  17         self.state_from = state_from
  18
  19     def set_inputs(self, inputs):
  20         self.inputs = inputs
  21         for k,v in inputs.items():
  22             setattr(self, k, v)
  23
  24     def set_outputs(self, outputs):
  25         self.outputs = outputs
  26         for k,v in outputs.items():
  27             setattr(self, k, v)
  28
  29
  30 class FPGetSyncOpsMod:
  31     def __init__(self, width, num_ops=2):
  32         self.width = width
  33         self.num_ops = num_ops
  34         inops = []
  35         outops = []
  36         for i in range(num_ops):
  37             inops.append(Signal(width, reset_less=True))
  38             outops.append(Signal(width, reset_less=True))
  39         self.in_op = inops
  40         self.out_op = outops
  41         self.stb = Signal(num_ops)
  42         self.ack = Signal()
  43         self.ready = Signal(reset_less=True)
  44         self.out_decode = Signal(reset_less=True)
  45
  46     def elaborate(self, platform):
  47         m = Module()
  48         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  49         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  50         with m.If(self.out_decode):
  51             for i in range(self.num_ops):
  52                 m.d.comb += [
  53                         self.out_op[i].eq(self.in_op[i]),
  54                 ]
  55         return m
  56
  57     def ports(self):
  58         return self.in_op + self.out_op + [self.stb, self.ack]
  59
  60
  61 class FPOps(Trigger):
  62     def __init__(self, width, num_ops):
  63         Trigger.__init__(self)
  64         self.width = width
  65         self.num_ops = num_ops
  66
  67         res = []
  68         for i in range(num_ops):
  69             res.append(Signal(width))
  70         self.v  = Array(res)
  71
  72     def ports(self):
  73         res = []
  74         for i in range(self.num_ops):
  75             res.append(self.v[i])
  76         res.append(self.ack)
  77         res.append(self.stb)
  78         return res
  79
  80
  81 class InputGroup:
  82     def __init__(self, width, num_ops=2, num_rows=4):
  83         self.width = width
  84         self.num_ops = num_ops
  85         self.num_rows = num_rows
  86         self.mmax = int(log(self.num_rows) / log(2))
  87         self.rs = []
  88         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  89         for i in range(num_rows):
  90             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  91         self.rs = Array(self.rs)
  92
  93         self.out_op = FPOps(width, num_ops)
  94
  95     def elaborate(self, platform):
  96         m = Module()
  97
  98         pe = PriorityEncoder(self.num_rows)
  99         m.submodules.selector = pe
 100         m.submodules.out_op = self.out_op
 101         m.submodules += self.rs
 102
 103         # connect priority encoder
 104         in_ready = []
 105         for i in range(self.num_rows):
 106             in_ready.append(self.rs[i].ready)
 107         m.d.comb += pe.i.eq(Cat(*in_ready))
 108
 109         active = Signal(reset_less=True)
 110         out_en = Signal(reset_less=True)
 111         m.d.comb += active.eq(~pe.n) # encoder active
 112         m.d.comb += out_en.eq(active & self.out_op.trigger)
 113
 114         # encoder active: ack relevant input, record MID, pass output
 115         with m.If(out_en):
 116             rs = self.rs[pe.o]
 117             m.d.sync += self.mid.eq(pe.o)
 118             m.d.sync += rs.ack.eq(0)
 119             m.d.sync += self.out_op.stb.eq(0)
 120             for j in range(self.num_ops):
 121                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 122         with m.Else():
 123             m.d.sync += self.out_op.stb.eq(1)
 124             # acks all default to zero
 125             for i in range(self.num_rows):
 126                 m.d.sync += self.rs[i].ack.eq(1)
 127
 128         return m
 129
 130     def ports(self):
 131         res = []
 132         for i in range(self.num_rows):
 133             inop = self.rs[i]
 134             res += inop.in_op + [inop.stb]
 135         return self.out_op.ports() + res + [self.mid]
 136
 137
 138 class FPGetOpMod:
 139     def __init__(self, width):
 140         self.in_op = FPOp(width)
 141         self.out_op = Signal(width)
 142         self.out_decode = Signal(reset_less=True)
 143
 144     def elaborate(self, platform):
 145         m = Module()
 146         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 147         m.submodules.get_op_in = self.in_op
 148         #m.submodules.get_op_out = self.out_op
 149         with m.If(self.out_decode):
 150             m.d.comb += [
 151                 self.out_op.eq(self.in_op.v),
 152             ]
 153         return m
 154
 155
 156 class FPGetOp(FPState):
 157     """ gets operand
 158     """
 159
 160     def __init__(self, in_state, out_state, in_op, width):
 161         FPState.__init__(self, in_state)
 162         self.out_state = out_state
 163         self.mod = FPGetOpMod(width)
 164         self.in_op = in_op
 165         self.out_op = Signal(width)
 166         self.out_decode = Signal(reset_less=True)
 167
 168     def setup(self, m, in_op):
 169         """ links module to inputs and outputs
 170         """
 171         setattr(m.submodules, self.state_from, self.mod)
 172         m.d.comb += self.mod.in_op.eq(in_op)
 173         #m.d.comb += self.out_op.eq(self.mod.out_op)
 174         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 175
 176     def action(self, m):
 177         with m.If(self.out_decode):
 178             m.next = self.out_state
 179             m.d.sync += [
 180                 self.in_op.ack.eq(0),
 181                 self.out_op.eq(self.mod.out_op)
 182             ]
 183         with m.Else():
 184             m.d.sync += self.in_op.ack.eq(1)
 185
 186
 187 class FPGet2OpMod(Trigger):
 188     def __init__(self, width, id_wid):
 189         Trigger.__init__(self)
 190         self.width = width
 191         self.id_wid = id_wid
 192         self.in_op1 = Signal(width, reset_less=True)
 193         self.in_op2 = Signal(width, reset_less=True)
 194         self.o = FPNumBase2Ops(width, id_wid)
 195
 196     def ospec(self):
 197         return FPNumBase2Ops(self.width, self.id_wid)
 198
 199     def elaborate(self, platform):
 200         m = Trigger.elaborate(self, platform)
 201         #m.submodules.get_op_in = self.in_op
 202         m.submodules.get_op1_out = self.o.a
 203         m.submodules.get_op2_out = self.o.b
 204         out_op1 = FPNumIn(None, self.width)
 205         out_op2 = FPNumIn(None, self.width)
 206         with m.If(self.trigger):
 207             m.d.comb += [
 208                 out_op1.decode(self.in_op1),
 209                 out_op2.decode(self.in_op2),
 210                 self.o.a.eq(out_op1),
 211                 self.o.b.eq(out_op2),
 212             ]
 213         return m
 214
 215
 216 class FPGet2Op(FPState):
 217     """ gets operands
 218     """
 219
 220     def __init__(self, in_state, out_state, in_op1, in_op2, width, id_wid):
 221         FPState.__init__(self, in_state)
 222         self.out_state = out_state
 223         self.mod = FPGet2OpMod(width, id_wid)
 224         self.in_op1 = in_op1
 225         self.in_op2 = in_op2
 226         self.o = self.mod.ospec()
 227         self.in_stb = Signal(reset_less=True)
 228         self.out_ack = Signal(reset_less=True)
 229         self.out_decode = Signal(reset_less=True)
 230
 231     def setup(self, m, in_op1, in_op2, in_stb, in_ack):
 232         """ links module to inputs and outputs
 233         """
 234         m.submodules.get_ops = self.mod
 235         m.d.comb += self.mod.in_op1.eq(in_op1)
 236         m.d.comb += self.mod.in_op2.eq(in_op2)
 237         m.d.comb += self.mod.stb.eq(in_stb)
 238         m.d.comb += self.out_ack.eq(self.mod.ack)
 239         m.d.comb += self.out_decode.eq(self.mod.trigger)
 240         m.d.comb += in_ack.eq(self.mod.ack)
 241
 242     def action(self, m):
 243         with m.If(self.out_decode):
 244             m.next = self.out_state
 245             m.d.sync += [
 246                 self.mod.ack.eq(0),
 247                 self.o.eq(self.mod.o),
 248             ]
 249         with m.Else():
 250             m.d.sync += self.mod.ack.eq(1)
 251
 252
 253 class FPNumBase2Ops:
 254
 255     def __init__(self, width, id_wid, m_extra=True):
 256         self.a = FPNumBase(width, m_extra)
 257         self.b = FPNumBase(width, m_extra)
 258         self.mid = Signal(id_wid, reset_less=True)
 259
 260     def eq(self, i):
 261         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 262
 263
 264 class FPAddSpecialCasesMod:
 265     """ special cases: NaNs, infs, zeros, denormalised
 266         NOTE: some of these are unique to add.  see "Special Operations"
 267         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 268     """
 269
 270     def __init__(self, width, id_wid):
 271         self.width = width
 272         self.id_wid = id_wid
 273         self.i = self.ispec()
 274         self.o = self.ospec()
 275         self.out_do_z = Signal(reset_less=True)
 276
 277     def ispec(self):
 278         return FPNumBase2Ops(self.width, self.id_wid)
 279
 280     def ospec(self):
 281         return FPPackData(self.width, self.id_wid)
 282
 283     def setup(self, m, i, out_do_z):
 284         """ links module to inputs and outputs
 285         """
 286         m.submodules.specialcases = self
 287         m.d.comb += self.i.eq(i)
 288         m.d.comb += out_do_z.eq(self.out_do_z)
 289
 290     def elaborate(self, platform):
 291         m = Module()
 292
 293         m.submodules.sc_in_a = self.i.a
 294         m.submodules.sc_in_b = self.i.b
 295         m.submodules.sc_out_z = self.o.z
 296
 297         s_nomatch = Signal()
 298         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 299
 300         m_match = Signal()
 301         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 302
 303         # if a is NaN or b is NaN return NaN
 304         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 305             m.d.comb += self.out_do_z.eq(1)
 306             m.d.comb += self.o.z.nan(0)
 307
 308         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 309         # under review
 310
 311         ## if a is zero and b is NaN return -b
 312         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 313         #    m.d.comb += self.out_do_z.eq(1)
 314         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 315
 316         ## if b is zero and a is NaN return -a
 317         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 318         #    m.d.comb += self.out_do_z.eq(1)
 319         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 320
 321         ## if a is -zero and b is NaN return -b
 322         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 323         #    m.d.comb += self.out_do_z.eq(1)
 324         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 325
 326         ## if b is -zero and a is NaN return -a
 327         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 328         #    m.d.comb += self.out_do_z.eq(1)
 329         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 330
 331         # if a is inf return inf (or NaN)
 332         with m.Elif(self.i.a.is_inf):
 333             m.d.comb += self.out_do_z.eq(1)
 334             m.d.comb += self.o.z.inf(self.i.a.s)
 335             # if a is inf and signs don't match return NaN
 336             with m.If(self.i.b.exp_128 & s_nomatch):
 337                 m.d.comb += self.o.z.nan(0)
 338
 339         # if b is inf return inf
 340         with m.Elif(self.i.b.is_inf):
 341             m.d.comb += self.out_do_z.eq(1)
 342             m.d.comb += self.o.z.inf(self.i.b.s)
 343
 344         # if a is zero and b zero return signed-a/b
 345         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 346             m.d.comb += self.out_do_z.eq(1)
 347             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 348                                           self.i.b.e,
 349                                           self.i.b.m[3:-1])
 350
 351         # if a is zero return b
 352         with m.Elif(self.i.a.is_zero):
 353             m.d.comb += self.out_do_z.eq(1)
 354             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 355                                       self.i.b.m[3:-1])
 356
 357         # if b is zero return a
 358         with m.Elif(self.i.b.is_zero):
 359             m.d.comb += self.out_do_z.eq(1)
 360             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 361                                       self.i.a.m[3:-1])
 362
 363         # if a equal to -b return zero (+ve zero)
 364         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 365             m.d.comb += self.out_do_z.eq(1)
 366             m.d.comb += self.o.z.zero(0)
 367
 368         # Denormalised Number checks
 369         with m.Else():
 370             m.d.comb += self.out_do_z.eq(0)
 371
 372         return m
 373
 374
 375 class FPID:
 376     def __init__(self, id_wid):
 377         self.id_wid = id_wid
 378         if self.id_wid:
 379             self.in_mid = Signal(id_wid, reset_less=True)
 380             self.out_mid = Signal(id_wid, reset_less=True)
 381         else:
 382             self.in_mid = None
 383             self.out_mid = None
 384
 385     def idsync(self, m):
 386         if self.id_wid is not None:
 387             m.d.sync += self.out_mid.eq(self.in_mid)
 388
 389
 390 class FPAddSpecialCases(FPState, FPID):
 391     """ special cases: NaNs, infs, zeros, denormalised
 392         NOTE: some of these are unique to add.  see "Special Operations"
 393         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 394     """
 395
 396     def __init__(self, width, id_wid):
 397         FPState.__init__(self, "special_cases")
 398         FPID.__init__(self, id_wid)
 399         self.mod = FPAddSpecialCasesMod(width)
 400         self.out_z = self.mod.ospec()
 401         self.out_do_z = Signal(reset_less=True)
 402
 403     def setup(self, m, in_a, in_b, in_mid):
 404         """ links module to inputs and outputs
 405         """
 406         self.mod.setup(m, in_a, in_b, self.out_do_z)
 407         if self.in_mid is not None:
 408             m.d.comb += self.in_mid.eq(in_mid)
 409
 410     def action(self, m):
 411         self.idsync(m)
 412         with m.If(self.out_do_z):
 413             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 414             m.next = "put_z"
 415         with m.Else():
 416             m.next = "denormalise"
 417
 418
 419 class FPAddSpecialCasesDeNorm(FPState, FPID):
 420     """ special cases: NaNs, infs, zeros, denormalised
 421         NOTE: some of these are unique to add.  see "Special Operations"
 422         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 423     """
 424
 425     def __init__(self, width, id_wid):
 426         FPState.__init__(self, "special_cases")
 427         FPID.__init__(self, id_wid)
 428         self.smod = FPAddSpecialCasesMod(width, id_wid)
 429         self.out_z = self.smod.ospec()
 430         self.out_do_z = Signal(reset_less=True)
 431
 432         self.dmod = FPAddDeNormMod(width, id_wid)
 433         self.o = self.dmod.ospec()
 434
 435     def setup(self, m, i, in_mid):
 436         """ links module to inputs and outputs
 437         """
 438         self.smod.setup(m, i, self.out_do_z)
 439         self.dmod.setup(m, i)
 440         if self.in_mid is not None:
 441             m.d.comb += self.in_mid.eq(in_mid)
 442
 443     def action(self, m):
 444         self.idsync(m)
 445         with m.If(self.out_do_z):
 446             m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 447             m.next = "put_z"
 448         with m.Else():
 449             m.next = "align"
 450             m.d.sync += self.o.a.eq(self.dmod.o.a)
 451             m.d.sync += self.o.b.eq(self.dmod.o.b)
 452
 453
 454 class FPAddDeNormMod(FPState):
 455
 456     def __init__(self, width, id_wid):
 457         self.width = width
 458         self.id_wid = id_wid
 459         self.i = self.ispec()
 460         self.o = self.ospec()
 461
 462     def ispec(self):
 463         return FPNumBase2Ops(self.width, self.id_wid)
 464
 465     def ospec(self):
 466         return FPNumBase2Ops(self.width, self.id_wid)
 467
 468     def setup(self, m, i):
 469         """ links module to inputs and outputs
 470         """
 471         m.submodules.denormalise = self
 472         m.d.comb += self.i.eq(i)
 473
 474     def elaborate(self, platform):
 475         m = Module()
 476         m.submodules.denorm_in_a = self.i.a
 477         m.submodules.denorm_in_b = self.i.b
 478         m.submodules.denorm_out_a = self.o.a
 479         m.submodules.denorm_out_b = self.o.b
 480         # hmmm, don't like repeating identical code
 481         m.d.comb += self.o.a.eq(self.i.a)
 482         with m.If(self.i.a.exp_n127):
 483             m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 484         with m.Else():
 485             m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 486
 487         m.d.comb += self.o.b.eq(self.i.b)
 488         with m.If(self.i.b.exp_n127):
 489             m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 490         with m.Else():
 491             m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 492
 493         return m
 494
 495
 496 class FPAddDeNorm(FPState, FPID):
 497
 498     def __init__(self, width, id_wid):
 499         FPState.__init__(self, "denormalise")
 500         FPID.__init__(self, id_wid)
 501         self.mod = FPAddDeNormMod(width)
 502         self.out_a = FPNumBase(width)
 503         self.out_b = FPNumBase(width)
 504
 505     def setup(self, m, in_a, in_b, in_mid):
 506         """ links module to inputs and outputs
 507         """
 508         self.mod.setup(m, in_a, in_b)
 509         if self.in_mid is not None:
 510             m.d.comb += self.in_mid.eq(in_mid)
 511
 512     def action(self, m):
 513         self.idsync(m)
 514         # Denormalised Number checks
 515         m.next = "align"
 516         m.d.sync += self.out_a.eq(self.mod.out_a)
 517         m.d.sync += self.out_b.eq(self.mod.out_b)
 518
 519
 520 class FPAddAlignMultiMod(FPState):
 521
 522     def __init__(self, width):
 523         self.in_a = FPNumBase(width)
 524         self.in_b = FPNumBase(width)
 525         self.out_a = FPNumIn(None, width)
 526         self.out_b = FPNumIn(None, width)
 527         self.exp_eq = Signal(reset_less=True)
 528
 529     def elaborate(self, platform):
 530         # This one however (single-cycle) will do the shift
 531         # in one go.
 532
 533         m = Module()
 534
 535         m.submodules.align_in_a = self.in_a
 536         m.submodules.align_in_b = self.in_b
 537         m.submodules.align_out_a = self.out_a
 538         m.submodules.align_out_b = self.out_b
 539
 540         # NOTE: this does *not* do single-cycle multi-shifting,
 541         #       it *STAYS* in the align state until exponents match
 542
 543         # exponent of a greater than b: shift b down
 544         m.d.comb += self.exp_eq.eq(0)
 545         m.d.comb += self.out_a.eq(self.in_a)
 546         m.d.comb += self.out_b.eq(self.in_b)
 547         agtb = Signal(reset_less=True)
 548         altb = Signal(reset_less=True)
 549         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 550         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 551         with m.If(agtb):
 552             m.d.comb += self.out_b.shift_down(self.in_b)
 553         # exponent of b greater than a: shift a down
 554         with m.Elif(altb):
 555             m.d.comb += self.out_a.shift_down(self.in_a)
 556         # exponents equal: move to next stage.
 557         with m.Else():
 558             m.d.comb += self.exp_eq.eq(1)
 559         return m
 560
 561
 562 class FPAddAlignMulti(FPState, FPID):
 563
 564     def __init__(self, width, id_wid):
 565         FPID.__init__(self, id_wid)
 566         FPState.__init__(self, "align")
 567         self.mod = FPAddAlignMultiMod(width)
 568         self.out_a = FPNumIn(None, width)
 569         self.out_b = FPNumIn(None, width)
 570         self.exp_eq = Signal(reset_less=True)
 571
 572     def setup(self, m, in_a, in_b, in_mid):
 573         """ links module to inputs and outputs
 574         """
 575         m.submodules.align = self.mod
 576         m.d.comb += self.mod.in_a.eq(in_a)
 577         m.d.comb += self.mod.in_b.eq(in_b)
 578         #m.d.comb += self.out_a.eq(self.mod.out_a)
 579         #m.d.comb += self.out_b.eq(self.mod.out_b)
 580         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 581         if self.in_mid is not None:
 582             m.d.comb += self.in_mid.eq(in_mid)
 583
 584     def action(self, m):
 585         self.idsync(m)
 586         m.d.sync += self.out_a.eq(self.mod.out_a)
 587         m.d.sync += self.out_b.eq(self.mod.out_b)
 588         with m.If(self.exp_eq):
 589             m.next = "add_0"
 590
 591
 592 class FPNumIn2Ops:
 593
 594     def __init__(self, width, id_wid):
 595         self.a = FPNumIn(None, width)
 596         self.b = FPNumIn(None, width)
 597         self.mid = Signal(id_wid, reset_less=True)
 598
 599     def eq(self, i):
 600         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 601
 602
 603 class FPAddAlignSingleMod:
 604
 605     def __init__(self, width, id_wid):
 606         self.width = width
 607         self.id_wid = id_wid
 608         self.i = self.ispec()
 609         self.o = self.ospec()
 610
 611     def ispec(self):
 612         return FPNumBase2Ops(self.width, self.id_wid)
 613
 614     def ospec(self):
 615         return FPNumIn2Ops(self.width, self.id_wid)
 616
 617     def setup(self, m, i):
 618         """ links module to inputs and outputs
 619         """
 620         m.submodules.align = self
 621         m.d.comb += self.i.eq(i)
 622
 623     def elaborate(self, platform):
 624         """ Aligns A against B or B against A, depending on which has the
 625             greater exponent.  This is done in a *single* cycle using
 626             variable-width bit-shift
 627
 628             the shifter used here is quite expensive in terms of gates.
 629             Mux A or B in (and out) into temporaries, as only one of them
 630             needs to be aligned against the other
 631         """
 632         m = Module()
 633
 634         m.submodules.align_in_a = self.i.a
 635         m.submodules.align_in_b = self.i.b
 636         m.submodules.align_out_a = self.o.a
 637         m.submodules.align_out_b = self.o.b
 638
 639         # temporary (muxed) input and output to be shifted
 640         t_inp = FPNumBase(self.width)
 641         t_out = FPNumIn(None, self.width)
 642         espec = (len(self.i.a.e), True)
 643         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 644         m.submodules.align_t_in = t_inp
 645         m.submodules.align_t_out = t_out
 646         m.submodules.multishift_r = msr
 647
 648         ediff = Signal(espec, reset_less=True)
 649         ediffr = Signal(espec, reset_less=True)
 650         tdiff = Signal(espec, reset_less=True)
 651         elz = Signal(reset_less=True)
 652         egz = Signal(reset_less=True)
 653
 654         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 655         m.d.comb += msr.inp.eq(t_inp.m)
 656         m.d.comb += msr.diff.eq(tdiff)
 657         m.d.comb += t_out.m.eq(msr.m)
 658         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 659         m.d.comb += t_out.s.eq(t_inp.s)
 660
 661         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 662         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 663         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 664         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 665
 666         # default: A-exp == B-exp, A and B untouched (fall through)
 667         m.d.comb += self.o.a.eq(self.i.a)
 668         m.d.comb += self.o.b.eq(self.i.b)
 669         # only one shifter (muxed)
 670         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 671         # exponent of a greater than b: shift b down
 672         with m.If(egz):
 673             m.d.comb += [t_inp.eq(self.i.b),
 674                          tdiff.eq(ediff),
 675                          self.o.b.eq(t_out),
 676                          self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 677                         ]
 678         # exponent of b greater than a: shift a down
 679         with m.Elif(elz):
 680             m.d.comb += [t_inp.eq(self.i.a),
 681                          tdiff.eq(ediffr),
 682                          self.o.a.eq(t_out),
 683                          self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 684                         ]
 685         return m
 686
 687
 688 class FPAddAlignSingle(FPState, FPID):
 689
 690     def __init__(self, width, id_wid):
 691         FPState.__init__(self, "align")
 692         FPID.__init__(self, id_wid)
 693         self.mod = FPAddAlignSingleMod(width, id_wid)
 694         self.out_a = FPNumIn(None, width)
 695         self.out_b = FPNumIn(None, width)
 696
 697     def setup(self, m, in_a, in_b, in_mid):
 698         """ links module to inputs and outputs
 699         """
 700         self.mod.setup(m, in_a, in_b)
 701         if self.in_mid is not None:
 702             m.d.comb += self.in_mid.eq(in_mid)
 703
 704     def action(self, m):
 705         self.idsync(m)
 706         # NOTE: could be done as comb
 707         m.d.sync += self.out_a.eq(self.mod.out_a)
 708         m.d.sync += self.out_b.eq(self.mod.out_b)
 709         m.next = "add_0"
 710
 711
 712 class FPAddAlignSingleAdd(FPState, FPID):
 713
 714     def __init__(self, width, id_wid):
 715         FPState.__init__(self, "align")
 716         FPID.__init__(self, id_wid)
 717         self.mod = FPAddAlignSingleMod(width, id_wid)
 718         self.o = self.mod.ospec()
 719
 720         self.a0mod = FPAddStage0Mod(width, id_wid)
 721         self.a0o = self.a0mod.ospec()
 722
 723         self.a1mod = FPAddStage1Mod(width, id_wid)
 724         self.a1o = self.a1mod.ospec()
 725
 726     def setup(self, m, i, in_mid):
 727         """ links module to inputs and outputs
 728         """
 729         self.mod.setup(m, i)
 730         m.d.comb += self.o.eq(self.mod.o)
 731
 732         self.a0mod.setup(m, self.o)
 733         m.d.comb += self.a0o.eq(self.a0mod.o)
 734
 735         self.a1mod.setup(m, self.a0o.tot, self.a0o.z)
 736
 737         if self.in_mid is not None:
 738             m.d.comb += self.in_mid.eq(in_mid)
 739
 740     def action(self, m):
 741         self.idsync(m)
 742         m.d.sync += self.a1o.eq(self.a1mod.o)
 743         m.next = "normalise_1"
 744
 745
 746 class FPAddStage0Data:
 747
 748     def __init__(self, width, id_wid):
 749         self.z = FPNumBase(width, False)
 750         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 751         self.mid = Signal(id_wid, reset_less=True)
 752
 753     def eq(self, i):
 754         return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
 755
 756
 757 class FPAddStage0Mod:
 758
 759     def __init__(self, width, id_wid):
 760         self.width = width
 761         self.id_wid = id_wid
 762         self.i = self.ispec()
 763         self.o = self.ospec()
 764
 765     def ispec(self):
 766         return FPNumBase2Ops(self.width, self.id_wid)
 767
 768     def ospec(self):
 769         return FPAddStage0Data(self.width, self.id_wid)
 770
 771     def setup(self, m, i):
 772         """ links module to inputs and outputs
 773         """
 774         m.submodules.add0 = self
 775         m.d.comb += self.i.eq(i)
 776
 777     def elaborate(self, platform):
 778         m = Module()
 779         m.submodules.add0_in_a = self.i.a
 780         m.submodules.add0_in_b = self.i.b
 781         m.submodules.add0_out_z = self.o.z
 782
 783         m.d.comb += self.o.z.e.eq(self.i.a.e)
 784
 785         # store intermediate tests (and zero-extended mantissas)
 786         seq = Signal(reset_less=True)
 787         mge = Signal(reset_less=True)
 788         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 789         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 790         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 791                      mge.eq(self.i.a.m >= self.i.b.m),
 792                      am0.eq(Cat(self.i.a.m, 0)),
 793                      bm0.eq(Cat(self.i.b.m, 0))
 794                     ]
 795         # same-sign (both negative or both positive) add mantissas
 796         with m.If(seq):
 797             m.d.comb += [
 798                 self.o.tot.eq(am0 + bm0),
 799                 self.o.z.s.eq(self.i.a.s)
 800             ]
 801         # a mantissa greater than b, use a
 802         with m.Elif(mge):
 803             m.d.comb += [
 804                 self.o.tot.eq(am0 - bm0),
 805                 self.o.z.s.eq(self.i.a.s)
 806             ]
 807         # b mantissa greater than a, use b
 808         with m.Else():
 809             m.d.comb += [
 810                 self.o.tot.eq(bm0 - am0),
 811                 self.o.z.s.eq(self.i.b.s)
 812         ]
 813         return m
 814
 815
 816 class FPAddStage0(FPState, FPID):
 817     """ First stage of add.  covers same-sign (add) and subtract
 818         special-casing when mantissas are greater or equal, to
 819         give greatest accuracy.
 820     """
 821
 822     def __init__(self, width, id_wid):
 823         FPState.__init__(self, "add_0")
 824         FPID.__init__(self, id_wid)
 825         self.mod = FPAddStage0Mod(width)
 826         self.o = self.mod.ospec()
 827
 828     def setup(self, m, in_a, in_b, in_mid):
 829         """ links module to inputs and outputs
 830         """
 831         self.mod.setup(m, in_a, in_b)
 832         if self.in_mid is not None:
 833             m.d.comb += self.in_mid.eq(in_mid)
 834
 835     def action(self, m):
 836         self.idsync(m)
 837         # NOTE: these could be done as combinatorial (merge add0+add1)
 838         m.d.sync += self.o.eq(self.mod.o)
 839         m.next = "add_1"
 840
 841
 842 class FPAddStage1Data:
 843
 844     def __init__(self, width, id_wid):
 845         self.z = FPNumBase(width, False)
 846         self.of = Overflow()
 847         self.mid = Signal(id_wid, reset_less=True)
 848
 849     def eq(self, i):
 850         return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
 851
 852
 853
 854 class FPAddStage1Mod(FPState):
 855     """ Second stage of add: preparation for normalisation.
 856         detects when tot sum is too big (tot[27] is kinda a carry bit)
 857     """
 858
 859     def __init__(self, width, id_wid):
 860         self.width = width
 861         self.id_wid = id_wid
 862         self.i = self.ispec()
 863         self.o = self.ospec()
 864
 865     def ispec(self):
 866         return FPAddStage0Data(self.width, self.id_wid)
 867
 868     def ospec(self):
 869         return FPAddStage1Data(self.width, self.id_wid)
 870
 871     def setup(self, m, in_tot, in_z):
 872         """ links module to inputs and outputs
 873         """
 874         m.submodules.add1 = self
 875         m.submodules.add1_out_overflow = self.o.of
 876
 877         m.d.comb += self.i.z.eq(in_z)
 878         m.d.comb += self.i.tot.eq(in_tot)
 879
 880     def elaborate(self, platform):
 881         m = Module()
 882         #m.submodules.norm1_in_overflow = self.in_of
 883         #m.submodules.norm1_out_overflow = self.out_of
 884         #m.submodules.norm1_in_z = self.in_z
 885         #m.submodules.norm1_out_z = self.out_z
 886         m.d.comb += self.o.z.eq(self.i.z)
 887         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 888         with m.If(self.i.tot[-1]):
 889             m.d.comb += [
 890                 self.o.z.m.eq(self.i.tot[4:]),
 891                 self.o.of.m0.eq(self.i.tot[4]),
 892                 self.o.of.guard.eq(self.i.tot[3]),
 893                 self.o.of.round_bit.eq(self.i.tot[2]),
 894                 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 895                 self.o.z.e.eq(self.i.z.e + 1)
 896         ]
 897         # tot[-1] (MSB) zero case
 898         with m.Else():
 899             m.d.comb += [
 900                 self.o.z.m.eq(self.i.tot[3:]),
 901                 self.o.of.m0.eq(self.i.tot[3]),
 902                 self.o.of.guard.eq(self.i.tot[2]),
 903                 self.o.of.round_bit.eq(self.i.tot[1]),
 904                 self.o.of.sticky.eq(self.i.tot[0])
 905         ]
 906         return m
 907
 908
 909 class FPAddStage1(FPState, FPID):
 910
 911     def __init__(self, width, id_wid):
 912         FPState.__init__(self, "add_1")
 913         FPID.__init__(self, id_wid)
 914         self.mod = FPAddStage1Mod(width)
 915         self.out_z = FPNumBase(width, False)
 916         self.out_of = Overflow()
 917         self.norm_stb = Signal()
 918
 919     def setup(self, m, in_tot, in_z, in_mid):
 920         """ links module to inputs and outputs
 921         """
 922         self.mod.setup(m, in_tot, in_z)
 923
 924         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 925
 926         if self.in_mid is not None:
 927             m.d.comb += self.in_mid.eq(in_mid)
 928
 929     def action(self, m):
 930         self.idsync(m)
 931         m.d.sync += self.out_of.eq(self.mod.out_of)
 932         m.d.sync += self.out_z.eq(self.mod.out_z)
 933         m.d.sync += self.norm_stb.eq(1)
 934         m.next = "normalise_1"
 935
 936
 937 class FPNormaliseModSingle:
 938
 939     def __init__(self, width):
 940         self.width = width
 941         self.in_z = self.ispec()
 942         self.out_z = self.ospec()
 943
 944     def ispec(self):
 945         return FPNumBase(self.width, False)
 946
 947     def ospec(self):
 948         return FPNumBase(self.width, False)
 949
 950     def setup(self, m, in_z, out_z):
 951         """ links module to inputs and outputs
 952         """
 953         m.submodules.normalise = self
 954         m.d.comb += self.in_z.eq(in_z)
 955         m.d.comb += out_z.eq(self.out_z)
 956
 957     def elaborate(self, platform):
 958         m = Module()
 959
 960         mwid = self.out_z.m_width+2
 961         pe = PriorityEncoder(mwid)
 962         m.submodules.norm_pe = pe
 963
 964         m.submodules.norm1_out_z = self.out_z
 965         m.submodules.norm1_in_z = self.in_z
 966
 967         in_z = FPNumBase(self.width, False)
 968         in_of = Overflow()
 969         m.submodules.norm1_insel_z = in_z
 970         m.submodules.norm1_insel_overflow = in_of
 971
 972         espec = (len(in_z.e), True)
 973         ediff_n126 = Signal(espec, reset_less=True)
 974         msr = MultiShiftRMerge(mwid, espec)
 975         m.submodules.multishift_r = msr
 976
 977         m.d.comb += in_z.eq(self.in_z)
 978         m.d.comb += in_of.eq(self.in_of)
 979         # initialise out from in (overridden below)
 980         m.d.comb += self.out_z.eq(in_z)
 981         m.d.comb += self.out_of.eq(in_of)
 982         # normalisation decrease condition
 983         decrease = Signal(reset_less=True)
 984         m.d.comb += decrease.eq(in_z.m_msbzero)
 985         # decrease exponent
 986         with m.If(decrease):
 987             # *sigh* not entirely obvious: count leading zeros (clz)
 988             # with a PriorityEncoder: to find from the MSB
 989             # we reverse the order of the bits.
 990             temp_m = Signal(mwid, reset_less=True)
 991             temp_s = Signal(mwid+1, reset_less=True)
 992             clz = Signal((len(in_z.e), True), reset_less=True)
 993             m.d.comb += [
 994                 # cat round and guard bits back into the mantissa
 995                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 996                 pe.i.eq(temp_m[::-1]),          # inverted
 997                 clz.eq(pe.o),                   # count zeros from MSB down
 998                 temp_s.eq(temp_m << clz),       # shift mantissa UP
 999                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
1000                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
1001             ]
1002
1003         return m
1004
1005 class FPNorm1Data:
1006
1007     def __init__(self, width, id_wid):
1008         self.roundz = Signal(reset_less=True)
1009         self.z = FPNumBase(width, False)
1010         self.mid = Signal(id_wid, reset_less=True)
1011
1012     def eq(self, i):
1013         return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1014
1015
1016 class FPNorm1ModSingle:
1017
1018     def __init__(self, width, id_wid):
1019         self.width = width
1020         self.id_wid = id_wid
1021         self.i = self.ispec()
1022         self.o = self.ospec()
1023
1024     def ispec(self):
1025         return FPAddStage1Data(self.width, self.id_wid)
1026
1027     def ospec(self):
1028         return FPNorm1Data(self.width, self.id_wid)
1029
1030     def setup(self, m, in_z, in_of, out_z):
1031         """ links module to inputs and outputs
1032         """
1033         m.submodules.normalise_1 = self
1034
1035         m.d.comb += self.i.z.eq(in_z)
1036         m.d.comb += self.i.of.eq(in_of)
1037
1038         m.d.comb += out_z.eq(self.o.z)
1039
1040     def elaborate(self, platform):
1041         m = Module()
1042
1043         mwid = self.o.z.m_width+2
1044         pe = PriorityEncoder(mwid)
1045         m.submodules.norm_pe = pe
1046
1047         of = Overflow()
1048         m.d.comb += self.o.roundz.eq(of.roundz)
1049
1050         m.submodules.norm1_out_z = self.o.z
1051         m.submodules.norm1_out_overflow = of
1052         m.submodules.norm1_in_z = self.i.z
1053         m.submodules.norm1_in_overflow = self.i.of
1054
1055         i = self.ispec()
1056         m.submodules.norm1_insel_z = i.z
1057         m.submodules.norm1_insel_overflow = i.of
1058
1059         espec = (len(i.z.e), True)
1060         ediff_n126 = Signal(espec, reset_less=True)
1061         msr = MultiShiftRMerge(mwid, espec)
1062         m.submodules.multishift_r = msr
1063
1064         m.d.comb += i.eq(self.i)
1065         # initialise out from in (overridden below)
1066         m.d.comb += self.o.z.eq(i.z)
1067         m.d.comb += of.eq(i.of)
1068         # normalisation increase/decrease conditions
1069         decrease = Signal(reset_less=True)
1070         increase = Signal(reset_less=True)
1071         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1072         m.d.comb += increase.eq(i.z.exp_lt_n126)
1073         # decrease exponent
1074         with m.If(decrease):
1075             # *sigh* not entirely obvious: count leading zeros (clz)
1076             # with a PriorityEncoder: to find from the MSB
1077             # we reverse the order of the bits.
1078             temp_m = Signal(mwid, reset_less=True)
1079             temp_s = Signal(mwid+1, reset_less=True)
1080             clz = Signal((len(i.z.e), True), reset_less=True)
1081             # make sure that the amount to decrease by does NOT
1082             # go below the minimum non-INF/NaN exponent
1083             limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1084                          i.z.exp_sub_n126)
1085             m.d.comb += [
1086                 # cat round and guard bits back into the mantissa
1087                 temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1088                 pe.i.eq(temp_m[::-1]),          # inverted
1089                 clz.eq(limclz),                 # count zeros from MSB down
1090                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1091                 self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1092                 self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1093                 of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1094                 # overflow in bits 0..1: got shifted too (leave sticky)
1095                 of.guard.eq(temp_s[1]),       # guard
1096                 of.round_bit.eq(temp_s[0]),   # round
1097             ]
1098         # increase exponent
1099         with m.Elif(increase):
1100             temp_m = Signal(mwid+1, reset_less=True)
1101             m.d.comb += [
1102                 temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1103                               i.z.m)),
1104                 ediff_n126.eq(i.z.N126 - i.z.e),
1105                 # connect multi-shifter to inp/out mantissa (and ediff)
1106                 msr.inp.eq(temp_m),
1107                 msr.diff.eq(ediff_n126),
1108                 self.o.z.m.eq(msr.m[3:]),
1109                 of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1110                 # overflow in bits 0..1: got shifted too (leave sticky)
1111                 of.guard.eq(temp_s[2]),     # guard
1112                 of.round_bit.eq(temp_s[1]), # round
1113                 of.sticky.eq(temp_s[0]),    # sticky
1114                 self.o.z.e.eq(i.z.e + ediff_n126),
1115             ]
1116
1117         return m
1118
1119
1120 class FPNorm1ModMulti:
1121
1122     def __init__(self, width, single_cycle=True):
1123         self.width = width
1124         self.in_select = Signal(reset_less=True)
1125         self.in_z = FPNumBase(width, False)
1126         self.in_of = Overflow()
1127         self.temp_z = FPNumBase(width, False)
1128         self.temp_of = Overflow()
1129         self.out_z = FPNumBase(width, False)
1130         self.out_of = Overflow()
1131
1132     def elaborate(self, platform):
1133         m = Module()
1134
1135         m.submodules.norm1_out_z = self.out_z
1136         m.submodules.norm1_out_overflow = self.out_of
1137         m.submodules.norm1_temp_z = self.temp_z
1138         m.submodules.norm1_temp_of = self.temp_of
1139         m.submodules.norm1_in_z = self.in_z
1140         m.submodules.norm1_in_overflow = self.in_of
1141
1142         in_z = FPNumBase(self.width, False)
1143         in_of = Overflow()
1144         m.submodules.norm1_insel_z = in_z
1145         m.submodules.norm1_insel_overflow = in_of
1146
1147         # select which of temp or in z/of to use
1148         with m.If(self.in_select):
1149             m.d.comb += in_z.eq(self.in_z)
1150             m.d.comb += in_of.eq(self.in_of)
1151         with m.Else():
1152             m.d.comb += in_z.eq(self.temp_z)
1153             m.d.comb += in_of.eq(self.temp_of)
1154         # initialise out from in (overridden below)
1155         m.d.comb += self.out_z.eq(in_z)
1156         m.d.comb += self.out_of.eq(in_of)
1157         # normalisation increase/decrease conditions
1158         decrease = Signal(reset_less=True)
1159         increase = Signal(reset_less=True)
1160         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1161         m.d.comb += increase.eq(in_z.exp_lt_n126)
1162         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1163         # decrease exponent
1164         with m.If(decrease):
1165             m.d.comb += [
1166                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1167                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1168                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1169                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1170                 self.out_of.round_bit.eq(0),        # reset round bit
1171                 self.out_of.m0.eq(in_of.guard),
1172             ]
1173         # increase exponent
1174         with m.Elif(increase):
1175             m.d.comb += [
1176                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1177                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1178                 self.out_of.guard.eq(in_z.m[0]),
1179                 self.out_of.m0.eq(in_z.m[1]),
1180                 self.out_of.round_bit.eq(in_of.guard),
1181                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1182             ]
1183
1184         return m
1185
1186
1187 class FPNorm1Single(FPState, FPID):
1188
1189     def __init__(self, width, id_wid, single_cycle=True):
1190         FPID.__init__(self, id_wid)
1191         FPState.__init__(self, "normalise_1")
1192         self.mod = FPNorm1ModSingle(width)
1193         self.out_z = FPNumBase(width, False)
1194         self.out_roundz = Signal(reset_less=True)
1195
1196     def setup(self, m, in_z, in_of, in_mid):
1197         """ links module to inputs and outputs
1198         """
1199         self.mod.setup(m, in_z, in_of, self.out_z)
1200
1201         if self.in_mid is not None:
1202             m.d.comb += self.in_mid.eq(in_mid)
1203
1204     def action(self, m):
1205         self.idsync(m)
1206         m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1207         m.next = "round"
1208
1209
1210 class FPNorm1Multi(FPState, FPID):
1211
1212     def __init__(self, width, id_wid):
1213         FPID.__init__(self, id_wid)
1214         FPState.__init__(self, "normalise_1")
1215         self.mod = FPNorm1ModMulti(width)
1216         self.stb = Signal(reset_less=True)
1217         self.ack = Signal(reset=0, reset_less=True)
1218         self.out_norm = Signal(reset_less=True)
1219         self.in_accept = Signal(reset_less=True)
1220         self.temp_z = FPNumBase(width)
1221         self.temp_of = Overflow()
1222         self.out_z = FPNumBase(width)
1223         self.out_roundz = Signal(reset_less=True)
1224
1225     def setup(self, m, in_z, in_of, norm_stb, in_mid):
1226         """ links module to inputs and outputs
1227         """
1228         self.mod.setup(m, in_z, in_of, norm_stb,
1229                        self.in_accept, self.temp_z, self.temp_of,
1230                        self.out_z, self.out_norm)
1231
1232         m.d.comb += self.stb.eq(norm_stb)
1233         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1234
1235         if self.in_mid is not None:
1236             m.d.comb += self.in_mid.eq(in_mid)
1237
1238     def action(self, m):
1239         self.idsync(m)
1240         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1241         m.d.sync += self.temp_of.eq(self.mod.out_of)
1242         m.d.sync += self.temp_z.eq(self.out_z)
1243         with m.If(self.out_norm):
1244             with m.If(self.in_accept):
1245                 m.d.sync += [
1246                     self.ack.eq(1),
1247                 ]
1248             with m.Else():
1249                 m.d.sync += self.ack.eq(0)
1250         with m.Else():
1251             # normalisation not required (or done).
1252             m.next = "round"
1253             m.d.sync += self.ack.eq(1)
1254             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1255
1256
1257 class FPNormToPack(FPState, FPID):
1258
1259     def __init__(self, width, id_wid):
1260         FPID.__init__(self, id_wid)
1261         FPState.__init__(self, "normalise_1")
1262         self.width = width
1263
1264     def setup(self, m, in_z, in_of, in_mid):
1265         """ links module to inputs and outputs
1266         """
1267
1268         # Normalisation (chained to input in_z+in_of)
1269         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1270         n_out = nmod.ospec()
1271         nmod.setup(m, in_z, in_of, n_out.z)
1272         m.d.comb += n_out.roundz.eq(nmod.o.roundz)
1273
1274         # Rounding (chained to normalisation)
1275         rmod = FPRoundMod(self.width, self.id_wid)
1276         r_out_z = rmod.ospec()
1277         rmod.setup(m, n_out.z, n_out.roundz)
1278         m.d.comb += r_out_z.eq(rmod.out_z)
1279
1280         # Corrections (chained to rounding)
1281         cmod = FPCorrectionsMod(self.width, self.id_wid)
1282         c_out_z = cmod.ospec()
1283         cmod.setup(m, r_out_z)
1284         m.d.comb += c_out_z.eq(cmod.out_z)
1285
1286         # Pack (chained to corrections)
1287         self.pmod = FPPackMod(self.width, self.id_wid)
1288         self.out_z = self.pmod.ospec()
1289         self.pmod.setup(m, c_out_z)
1290
1291         # Multiplex ID
1292         if self.in_mid is not None:
1293             m.d.comb += self.in_mid.eq(in_mid)
1294
1295     def action(self, m):
1296         self.idsync(m) # copies incoming ID to outgoing
1297         m.d.sync += self.out_z.z.v.eq(self.pmod.o.z.v) # outputs packed result
1298         m.next = "pack_put_z"
1299
1300
1301 class FPRoundData:
1302
1303     def __init__(self, width, id_wid):
1304         self.z = FPNumBase(width, False)
1305         self.mid = Signal(id_wid, reset_less=True)
1306
1307     def eq(self, i):
1308         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1309
1310
1311 class FPRoundMod:
1312
1313     def __init__(self, width, id_wid):
1314         self.width = width
1315         self.id_wid = id_wid
1316         self.i = self.ispec()
1317         self.out_z = self.ospec()
1318
1319     def ispec(self):
1320         return FPNorm1Data(self.width, self.id_wid)
1321
1322     def ospec(self):
1323         return FPRoundData(self.width, self.id_wid)
1324
1325     def setup(self, m, in_z, roundz):
1326         m.submodules.roundz = self
1327
1328         m.d.comb += self.i.z.eq(in_z)
1329         m.d.comb += self.i.roundz.eq(roundz)
1330
1331     def elaborate(self, platform):
1332         m = Module()
1333         m.d.comb += self.out_z.eq(self.i)
1334         with m.If(self.i.roundz):
1335             m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
1336             with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1337                 m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1338         return m
1339
1340
1341 class FPRound(FPState, FPID):
1342
1343     def __init__(self, width, id_wid):
1344         FPState.__init__(self, "round")
1345         FPID.__init__(self, id_wid)
1346         self.mod = FPRoundMod(width)
1347         self.out_z = self.mod.ospec()
1348
1349     def setup(self, m, in_z, roundz, in_mid):
1350         """ links module to inputs and outputs
1351         """
1352         self.mod.setup(m, in_z, roundz)
1353
1354         if self.in_mid is not None:
1355             m.d.comb += self.in_mid.eq(in_mid)
1356
1357     def action(self, m):
1358         self.idsync(m)
1359         m.d.sync += self.out_z.eq(self.mod.out_z)
1360         m.next = "corrections"
1361
1362
1363 class FPCorrectionsMod:
1364
1365     def __init__(self, width, id_wid):
1366         self.width = width
1367         self.id_wid = id_wid
1368         self.in_z = self.ispec()
1369         self.out_z = self.ospec()
1370
1371     def ispec(self):
1372         return FPRoundData(self.width, self.id_wid)
1373
1374     def ospec(self):
1375         return FPRoundData(self.width, self.id_wid)
1376
1377     def setup(self, m, in_z):
1378         """ links module to inputs and outputs
1379         """
1380         m.submodules.corrections = self
1381         m.d.comb += self.in_z.eq(in_z)
1382
1383     def elaborate(self, platform):
1384         m = Module()
1385         m.submodules.corr_in_z = self.in_z.z
1386         m.submodules.corr_out_z = self.out_z.z
1387         m.d.comb += self.out_z.eq(self.in_z)
1388         with m.If(self.in_z.z.is_denormalised):
1389             m.d.comb += self.out_z.z.e.eq(self.in_z.z.N127)
1390         return m
1391
1392
1393 class FPCorrections(FPState, FPID):
1394
1395     def __init__(self, width, id_wid):
1396         FPState.__init__(self, "corrections")
1397         FPID.__init__(self, id_wid)
1398         self.mod = FPCorrectionsMod(width)
1399         self.out_z = self.mod.ospec()
1400
1401     def setup(self, m, in_z, in_mid):
1402         """ links module to inputs and outputs
1403         """
1404         self.mod.setup(m, in_z)
1405         if self.in_mid is not None:
1406             m.d.comb += self.in_mid.eq(in_mid)
1407
1408     def action(self, m):
1409         self.idsync(m)
1410         m.d.sync += self.out_z.eq(self.mod.out_z)
1411         m.next = "pack"
1412
1413
1414 class FPPackData:
1415
1416     def __init__(self, width, id_wid):
1417         self.z = FPNumOut(width, False)
1418         self.mid = Signal(id_wid, reset_less=True)
1419
1420     def eq(self, i):
1421         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1422
1423
1424 class FPPackMod:
1425
1426     def __init__(self, width, id_wid):
1427         self.width = width
1428         self.id_wid = id_wid
1429         self.i = self.ispec()
1430         self.o = self.ospec()
1431
1432     def ispec(self):
1433         return FPRoundData(self.width, self.id_wid)
1434
1435     def ospec(self):
1436         return FPPackData(self.width, self.id_wid)
1437
1438     def setup(self, m, in_z):
1439         """ links module to inputs and outputs
1440         """
1441         m.submodules.pack = self
1442         m.d.comb += self.i.eq(in_z)
1443
1444     def elaborate(self, platform):
1445         m = Module()
1446         m.submodules.pack_in_z = self.i.z
1447         with m.If(self.i.z.is_overflowed):
1448             m.d.comb += self.o.z.inf(self.i.z.s)
1449         with m.Else():
1450             m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1451         return m
1452
1453
1454 class FPPackData:
1455     def __init__(self, width, id_wid):
1456         self.z = FPNumOut(width, False)
1457         self.mid = Signal(id_wid, reset_less=True)
1458
1459     def eq(self, i):
1460         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1461
1462
1463 class FPPack(FPState, FPID):
1464
1465     def __init__(self, width, id_wid):
1466         FPState.__init__(self, "pack")
1467         FPID.__init__(self, id_wid)
1468         self.mod = FPPackMod(width)
1469         self.out_z = self.ospec()
1470
1471     def ispec(self):
1472         return self.mod.ispec()
1473
1474     def ospec(self):
1475         return self.mod.ospec()
1476
1477     def setup(self, m, in_z, in_mid):
1478         """ links module to inputs and outputs
1479         """
1480         self.mod.setup(m, in_z)
1481         if self.in_mid is not None:
1482             m.d.comb += self.in_mid.eq(in_mid)
1483
1484     def action(self, m):
1485         self.idsync(m)
1486         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1487         m.next = "pack_put_z"
1488
1489
1490 class FPPutZ(FPState):
1491
1492     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1493         FPState.__init__(self, state)
1494         if to_state is None:
1495             to_state = "get_ops"
1496         self.to_state = to_state
1497         self.in_z = in_z
1498         self.out_z = out_z
1499         self.in_mid = in_mid
1500         self.out_mid = out_mid
1501
1502     def action(self, m):
1503         if self.in_mid is not None:
1504             m.d.sync += self.out_mid.eq(self.in_mid)
1505         m.d.sync += [
1506           self.out_z.v.eq(self.in_z.v)
1507         ]
1508         with m.If(self.out_z.stb & self.out_z.ack):
1509             m.d.sync += self.out_z.stb.eq(0)
1510             m.next = self.to_state
1511         with m.Else():
1512             m.d.sync += self.out_z.stb.eq(1)
1513
1514
1515 class FPPutZIdx(FPState):
1516
1517     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1518         FPState.__init__(self, state)
1519         if to_state is None:
1520             to_state = "get_ops"
1521         self.to_state = to_state
1522         self.in_z = in_z
1523         self.out_zs = out_zs
1524         self.in_mid = in_mid
1525
1526     def action(self, m):
1527         outz_stb = Signal(reset_less=True)
1528         outz_ack = Signal(reset_less=True)
1529         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1530                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1531                     ]
1532         m.d.sync += [
1533           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1534         ]
1535         with m.If(outz_stb & outz_ack):
1536             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1537             m.next = self.to_state
1538         with m.Else():
1539             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1540
1541
1542 class FPADDBaseMod(FPID):
1543
1544     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1545         """ IEEE754 FP Add
1546
1547             * width: bit-width of IEEE754.  supported: 16, 32, 64
1548             * id_wid: an identifier that is sync-connected to the input
1549             * single_cycle: True indicates each stage to complete in 1 clock
1550             * compact: True indicates a reduced number of stages
1551         """
1552         FPID.__init__(self, id_wid)
1553         self.width = width
1554         self.single_cycle = single_cycle
1555         self.compact = compact
1556
1557         self.in_t = Trigger()
1558         self.in_a  = Signal(width)
1559         self.in_b  = Signal(width)
1560         self.out_z = FPOp(width)
1561
1562         self.states = []
1563
1564     def add_state(self, state):
1565         self.states.append(state)
1566         return state
1567
1568     def get_fragment(self, platform=None):
1569         """ creates the HDL code-fragment for FPAdd
1570         """
1571         m = Module()
1572         m.submodules.out_z = self.out_z
1573         m.submodules.in_t = self.in_t
1574         if self.compact:
1575             self.get_compact_fragment(m, platform)
1576         else:
1577             self.get_longer_fragment(m, platform)
1578
1579         with m.FSM() as fsm:
1580
1581             for state in self.states:
1582                 with m.State(state.state_from):
1583                     state.action(m)
1584
1585         return m
1586
1587     def get_longer_fragment(self, m, platform=None):
1588
1589         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1590                                       self.in_a, self.in_b, self.width))
1591         get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1592         a = get.out_op1
1593         b = get.out_op2
1594
1595         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1596         sc.setup(m, a, b, self.in_mid)
1597
1598         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1599         dn.setup(m, a, b, sc.in_mid)
1600
1601         if self.single_cycle:
1602             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1603             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1604         else:
1605             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1606             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1607
1608         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1609         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1610
1611         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1612         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1613
1614         if self.single_cycle:
1615             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1616             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1617         else:
1618             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1619             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1620
1621         rn = self.add_state(FPRound(self.width, self.id_wid))
1622         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1623
1624         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1625         cor.setup(m, rn.out_z, rn.in_mid)
1626
1627         pa = self.add_state(FPPack(self.width, self.id_wid))
1628         pa.setup(m, cor.out_z, rn.in_mid)
1629
1630         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1631                                     pa.in_mid, self.out_mid))
1632
1633         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1634                                     pa.in_mid, self.out_mid))
1635
1636     def get_compact_fragment(self, m, platform=None):
1637
1638         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1639                                       self.in_a, self.in_b,
1640                                       self.width, self.id_wid))
1641         get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1642         a = get.o.a
1643         b = get.o.b
1644
1645         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1646         sc.setup(m, get.o, self.in_mid)
1647
1648         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1649         alm.setup(m, sc.o, sc.in_mid)
1650
1651         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1652         n1.setup(m, alm.a1o.z, alm.a1o.of, alm.in_mid)
1653
1654         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.out_z,
1655                                     n1.in_mid, self.out_mid))
1656
1657         pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.out_z,
1658                                     sc.in_mid, self.out_mid))
1659
1660
1661 class FPADDBase(FPState, FPID):
1662
1663     def __init__(self, width, id_wid=None, single_cycle=False):
1664         """ IEEE754 FP Add
1665
1666             * width: bit-width of IEEE754.  supported: 16, 32, 64
1667             * id_wid: an identifier that is sync-connected to the input
1668             * single_cycle: True indicates each stage to complete in 1 clock
1669         """
1670         FPID.__init__(self, id_wid)
1671         FPState.__init__(self, "fpadd")
1672         self.width = width
1673         self.single_cycle = single_cycle
1674         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1675
1676         self.in_t = Trigger()
1677         self.in_a  = Signal(width)
1678         self.in_b  = Signal(width)
1679         #self.out_z = FPOp(width)
1680
1681         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1682         self.in_accept = Signal(reset_less=True)
1683         self.add_stb = Signal(reset_less=True)
1684         self.add_ack = Signal(reset=0, reset_less=True)
1685
1686     def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1687         self.out_z = out_z
1688         self.out_mid = out_mid
1689         m.d.comb += [self.in_a.eq(a),
1690                      self.in_b.eq(b),
1691                      self.mod.in_a.eq(self.in_a),
1692                      self.mod.in_b.eq(self.in_b),
1693                      self.in_mid.eq(in_mid),
1694                      self.mod.in_mid.eq(self.in_mid),
1695                      self.z_done.eq(self.mod.out_z.trigger),
1696                      #self.add_stb.eq(add_stb),
1697                      self.mod.in_t.stb.eq(self.in_t.stb),
1698                      self.in_t.ack.eq(self.mod.in_t.ack),
1699                      self.out_mid.eq(self.mod.out_mid),
1700                      self.out_z.v.eq(self.mod.out_z.v),
1701                      self.out_z.stb.eq(self.mod.out_z.stb),
1702                      self.mod.out_z.ack.eq(self.out_z.ack),
1703                     ]
1704
1705         m.d.sync += self.add_stb.eq(add_stb)
1706         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1707         m.d.sync += self.out_z.ack.eq(0) # likewise
1708         #m.d.sync += self.in_t.stb.eq(0)
1709
1710         m.submodules.fpadd = self.mod
1711
1712     def action(self, m):
1713
1714         # in_accept is set on incoming strobe HIGH and ack LOW.
1715         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1716
1717         #with m.If(self.in_t.ack):
1718         #    m.d.sync += self.in_t.stb.eq(0)
1719         with m.If(~self.z_done):
1720             # not done: test for accepting an incoming operand pair
1721             with m.If(self.in_accept):
1722                 m.d.sync += [
1723                     self.add_ack.eq(1), # acknowledge receipt...
1724                     self.in_t.stb.eq(1), # initiate add
1725                 ]
1726             with m.Else():
1727                 m.d.sync += [self.add_ack.eq(0),
1728                              self.in_t.stb.eq(0),
1729                              self.out_z.ack.eq(1),
1730                             ]
1731         with m.Else():
1732             # done: acknowledge, and write out id and value
1733             m.d.sync += [self.add_ack.eq(1),
1734                          self.in_t.stb.eq(0)
1735                         ]
1736             m.next = "put_z"
1737
1738             return
1739
1740             if self.in_mid is not None:
1741                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1742
1743             m.d.sync += [
1744               self.out_z.v.eq(self.mod.out_z.v)
1745             ]
1746             # move to output state on detecting z ack
1747             with m.If(self.out_z.trigger):
1748                 m.d.sync += self.out_z.stb.eq(0)
1749                 m.next = "put_z"
1750             with m.Else():
1751                 m.d.sync += self.out_z.stb.eq(1)
1752
1753 class ResArray:
1754     def __init__(self, width, id_wid):
1755         self.width = width
1756         self.id_wid = id_wid
1757         res = []
1758         for i in range(rs_sz):
1759             out_z = FPOp(width)
1760             out_z.name = "out_z_%d" % i
1761             res.append(out_z)
1762         self.res = Array(res)
1763         self.in_z = FPOp(width)
1764         self.in_mid = Signal(self.id_wid, reset_less=True)
1765
1766     def setup(self, m, in_z, in_mid):
1767         m.d.comb += [self.in_z.eq(in_z),
1768                      self.in_mid.eq(in_mid)]
1769
1770     def get_fragment(self, platform=None):
1771         """ creates the HDL code-fragment for FPAdd
1772         """
1773         m = Module()
1774         m.submodules.res_in_z = self.in_z
1775         m.submodules += self.res
1776
1777         return m
1778
1779     def ports(self):
1780         res = []
1781         for z in self.res:
1782             res += z.ports()
1783         return res
1784
1785
1786 class FPADD(FPID):
1787     """ FPADD: stages as follows:
1788
1789         FPGetOp (a)
1790            |
1791         FPGetOp (b)
1792            |
1793         FPAddBase---> FPAddBaseMod
1794            |            |
1795         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1796
1797         FPAddBase is tricky: it is both a stage and *has* stages.
1798         Connection to FPAddBaseMod therefore requires an in stb/ack
1799         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1800         needs to be the thing that raises the incoming stb.
1801     """
1802
1803     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1804         """ IEEE754 FP Add
1805
1806             * width: bit-width of IEEE754.  supported: 16, 32, 64
1807             * id_wid: an identifier that is sync-connected to the input
1808             * single_cycle: True indicates each stage to complete in 1 clock
1809         """
1810         self.width = width
1811         self.id_wid = id_wid
1812         self.single_cycle = single_cycle
1813
1814         #self.out_z = FPOp(width)
1815         self.ids = FPID(id_wid)
1816
1817         rs = []
1818         for i in range(rs_sz):
1819             in_a  = FPOp(width)
1820             in_b  = FPOp(width)
1821             in_a.name = "in_a_%d" % i
1822             in_b.name = "in_b_%d" % i
1823             rs.append((in_a, in_b))
1824         self.rs = Array(rs)
1825
1826         res = []
1827         for i in range(rs_sz):
1828             out_z = FPOp(width)
1829             out_z.name = "out_z_%d" % i
1830             res.append(out_z)
1831         self.res = Array(res)
1832
1833         self.states = []
1834
1835     def add_state(self, state):
1836         self.states.append(state)
1837         return state
1838
1839     def get_fragment(self, platform=None):
1840         """ creates the HDL code-fragment for FPAdd
1841         """
1842         m = Module()
1843         m.submodules += self.rs
1844
1845         in_a = self.rs[0][0]
1846         in_b = self.rs[0][1]
1847
1848         out_z = FPOp(self.width)
1849         out_mid = Signal(self.id_wid, reset_less=True)
1850         m.submodules.out_z = out_z
1851
1852         geta = self.add_state(FPGetOp("get_a", "get_b",
1853                                       in_a, self.width))
1854         geta.setup(m, in_a)
1855         a = geta.out_op
1856
1857         getb = self.add_state(FPGetOp("get_b", "fpadd",
1858                                       in_b, self.width))
1859         getb.setup(m, in_b)
1860         b = getb.out_op
1861
1862         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1863         ab = self.add_state(ab)
1864         ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1865                  out_z, out_mid)
1866
1867         pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1868                                     out_mid, "get_a"))
1869
1870         with m.FSM() as fsm:
1871
1872             for state in self.states:
1873                 with m.State(state.state_from):
1874                     state.action(m)
1875
1876         return m
1877
1878
1879 if __name__ == "__main__":
1880     if True:
1881         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1882         main(alu, ports=alu.rs[0][0].ports() + \
1883                         alu.rs[0][1].ports() + \
1884                         alu.res[0].ports() + \
1885                         [alu.ids.in_mid, alu.ids.out_mid])
1886     else:
1887         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1888         main(alu, ports=[alu.in_a, alu.in_b] + \
1889                         alu.in_t.ports() + \
1890                         alu.out_z.ports() + \
1891                         [alu.in_mid, alu.out_mid])
1892
1893
1894     # works... but don't use, just do "python fname.py convert -t v"
1895     #print (verilog.convert(alu, ports=[
1896     #                        ports=alu.in_a.ports() + \
1897     #                              alu.in_b.ports() + \
1898     #                              alu.out_z.ports())