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[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat
6 from nmigen.cli import main
7
8
9 class FPADD:
10 def __init__(self, width):
11 self.width = width
12
13 self.in_a = Signal(width)
14 self.in_a_stb = Signal()
15 self.in_a_ack = Signal()
16
17 self.in_b = Signal(width)
18 self.in_b_stb = Signal()
19 self.in_b_ack = Signal()
20
21 self.out_z = Signal(width)
22 self.out_z_stb = Signal()
23 self.out_z_ack = Signal()
24
25 s_out_z_stb = Signal()
26 s_out_z = Signal(width)
27 s_in_a_ack = Signal()
28 s_in_b_ack = Signal()
29
30 def get_fragment(self, platform):
31 m = Module()
32
33 # Latches
34 a = Signal(self.width)
35 b = Signal(self.width)
36 z = Signal(self.width)
37
38 # Mantissa
39 a_m = Signal(27) # ??? seems to be 1 bit extra??
40 b_m = Signal(27) # ??? seems to be 1 bit extra??
41 z_m = Signal(24)
42
43 # Exponent
44 a_e = Signal(10)
45 b_e = Signal(10)
46 z_e = Signal(10)
47
48 # Sign
49 a_s = Signal()
50 b_s = Signal()
51 z_s = Signal()
52
53 guard = Signal()
54 round_bit = Signal()
55 sticky = Signal()
56
57 tot = Signal(28)
58
59 with m.FSM() as fsm:
60
61 # ******
62 # gets operand a
63
64 with m.State("get_a"):
65 with m.If((self.in_a_ack) & (self.in_a_stb)):
66 m.next = "get_b"
67 m.d.sync += [
68 a.eq(self.in_a),
69 self.in_a_ack.eq(0)
70 ]
71 with m.Else():
72 m.d.sync += self.in_a_ack.eq(1)
73
74 # ******
75 # gets operand b
76
77 with m.State("get_b"):
78 with m.If((self.in_b_ack) & (self.in_b_stb)):
79 m.next = "get_a"
80 m.d.sync += [
81 b.eq(self.in_b),
82 self.in_b_ack.eq(0)
83 ]
84 with m.Else():
85 m.d.sync += self.in_b_ack.eq(1)
86
87 # ******
88 # unpacks operands into sign, mantissa and exponent
89
90 with m.State("unpack"):
91 m.next = "special_cases"
92 m.d.sync += [
93 # mantissa
94 a_m.eq(Cat(0, 0, 0, a[0:23])),
95 b_m.eq(Cat(0, 0, 0, b[0:23])),
96 # exponent (take off exponent bias, here)
97 a_e.eq(Cat(a[23:31]) - 127),
98 b_e.eq(Cat(b[23:31]) - 127),
99 # sign
100 a_s.eq(Cat(a[31])),
101 b_s.eq(Cat(b[31]))
102 ]
103
104 # ******
105 # special cases: NaNs, infs, zeros, denormalised
106
107 with m.State("special_cases"):
108
109 # if a is NaN or b is NaN return NaN
110 with m.If(((a_e == 128) & (a_m != 0)) | \
111 ((b_e == 128) & (b_m != 0))):
112 m.next = "put_z"
113 m.d.sync += [
114 z[31].eq(1), # sign: 1
115 z[23:31].eq(255), # exp: 0b11111...
116 z[22].eq(1), # mantissa top bit: 1
117 z[0:22].eq(0) # mantissa rest: 0b0000...
118 ]
119
120 # if a is inf return inf (or NaN)
121 with m.Elif(a_e == 128):
122 m.next = "put_z"
123 m.d.sync += [
124 z[31].eq(a_s), # sign: a_s
125 z[23:31].eq(255), # exp: 0b11111...
126 z[0:23].eq(0) # mantissa rest: 0b0000...
127 ]
128 # if a is inf and signs don't match return NaN
129 with m.If((b_e == 128) & (a_s != b_s)):
130 m.d.sync += [
131 z[31].eq(b_s), # sign: b_s
132 z[23:31].eq(255), # exp: 0b11111...
133 z[22].eq(1), # mantissa top bit: 1
134 z[0:22].eq(0) # mantissa rest: 0b0000...
135 ]
136 # if b is inf return inf
137 with m.Elif(b_e == 128):
138 m.next = "put_z"
139 m.d.sync += [
140 z[31].eq(b_s), # sign: b_s
141 z[23:31].eq(255), # exp: 0b11111...
142 z[0:23].eq(0) # mantissa rest: 0b0000...
143 ]
144
145 # if a is zero and b zero return signed-a/b
146 with m.Elif(((a_e == -127) & (a_m == 0)) & \
147 ((b_e == -127) & (b_m == 0))):
148 m.next = "put_z"
149 m.d.sync += [
150 z[31].eq(a_s & b_s), # sign: a/b_s
151 z[23:31].eq(b_e[0:8] + 127), # exp: b_e (plus bias)
152 z[0:23].eq(b_m[3:26]) # mantissa: b_m top bits
153 ]
154
155 # if a is zero return b
156 with m.Elif((a_e == -127) & (a_m == 0)):
157 m.next = "put_z"
158 m.d.sync += [
159 z[31].eq(b_s), # sign: a/b_s
160 z[23:31].eq(b_e[0:8] + 127), # exp: b_e (plus bias)
161 z[0:23].eq(b_m[3:26]) # mantissa: b_m top bits
162 ]
163
164 # if b is zero return a
165 with m.Elif((b_e == -127) & (b_m == 0)):
166 m.next = "put_z"
167 m.d.sync += [
168 z[31].eq(a_s), # sign: a/b_s
169 z[23:31].eq(a_e[0:8] + 127), # exp: a_e (plus bias)
170 z[0:23].eq(a_m[3:26]) # mantissa: a_m top bits
171 ]
172
173 # Denormalised Number checks
174 with m.Else():
175 m.next = "align"
176 # denormalise a check
177 with m.If(a_e == -127):
178 m.d.sync += a_e.eq(-126) # limit a exponent
179 with m.Else():
180 m.d.sync += a_m[26].eq(1) # set highest mantissa bit
181 # denormalise b check
182 with m.If(b_e == -127):
183 m.d.sync += b_e.eq(-126) # limit b exponent
184 with m.Else():
185 m.d.sync += b_m[26].eq(1) # set highest mantissa bit
186
187 # First stage of add
188 with m.State("add_0"):
189 m.next = "add_1"
190 m.d.sync += z_e.eq(a_e)
191 # same-sign (both negative or both positive) add mantissas
192 with m.If(a_s == b_s):
193 m.d.sync += [
194 tot.eq(a_m + b_m),
195 z_s.eq(a_s)
196 ]
197 # a mantissa greater than b, use a
198 with m.Else(a_m >= b_m):
199 m.d.sync += [
200 tot.eq(a_m - b_m),
201 z_s.eq(a_s)
202 ]
203 # b mantissa greater than a, use b
204 with m.Else():
205 m.sync += [
206 tot.eq(b_m - a_m),
207 z_s.eq(b_s)
208 ]
209 return m
210
211 """
212 always @(posedge clk)
213 begin
214
215 case(state)
216
217 get_a:
218 begin
219 s_in_a_ack <= 1;
220 if (s_in_a_ack && in_a_stb) begin
221 a <= in_a;
222 s_in_a_ack <= 0;
223 state <= get_b;
224 end
225 end
226
227 get_b:
228 begin
229 s_in_b_ack <= 1;
230 if (s_in_b_ack && in_b_stb) begin
231 b <= in_b;
232 s_in_b_ack <= 0;
233 state <= unpack;
234 end
235 end
236
237 unpack:
238 begin
239 a_m <= {a[22 : 0], 3'd0};
240 b_m <= {b[22 : 0], 3'd0};
241 a_e <= a[30 : 23] - 127;
242 b_e <= b[30 : 23] - 127;
243 a_s <= a[31];
244 b_s <= b[31];
245 state <= special_cases;
246 end
247
248 special_cases:
249 begin
250 //if a is NaN or b is NaN return NaN
251 if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
252 z[31] <= 1;
253 z[30:23] <= 255;
254 z[22] <= 1;
255 z[21:0] <= 0;
256 state <= put_z;
257 //if a is inf return inf
258 end else if (a_e == 128) begin
259 z[31] <= a_s;
260 z[30:23] <= 255;
261 z[22:0] <= 0;
262 //if a is inf and signs don't match return nan
263 if ((b_e == 128) && (a_s != b_s)) begin
264 z[31] <= b_s;
265 z[30:23] <= 255;
266 z[22] <= 1;
267 z[21:0] <= 0;
268 end
269 state <= put_z;
270 //if b is inf return inf
271 end else if (b_e == 128) begin
272 z[31] <= b_s;
273 z[30:23] <= 255;
274 z[22:0] <= 0;
275 state <= put_z;
276 //if a is zero return b
277 end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
278 z[31] <= a_s & b_s;
279 z[30:23] <= b_e[7:0] + 127;
280 z[22:0] <= b_m[26:3];
281 state <= put_z;
282 //if a is zero return b
283 end else if (($signed(a_e) == -127) && (a_m == 0)) begin
284 z[31] <= b_s;
285 z[30:23] <= b_e[7:0] + 127;
286 z[22:0] <= b_m[26:3];
287 state <= put_z;
288 //if b is zero return a
289 end else if (($signed(b_e) == -127) && (b_m == 0)) begin
290 z[31] <= a_s;
291 z[30:23] <= a_e[7:0] + 127;
292 z[22:0] <= a_m[26:3];
293 state <= put_z;
294 end else begin
295 //Denormalised Number
296 if ($signed(a_e) == -127) begin
297 a_e <= -126;
298 end else begin
299 a_m[26] <= 1;
300 end
301 //Denormalised Number
302 if ($signed(b_e) == -127) begin
303 b_e <= -126;
304 end else begin
305 b_m[26] <= 1;
306 end
307 state <= align;
308 end
309 end
310
311 align:
312 begin
313 if ($signed(a_e) > $signed(b_e)) begin
314 b_e <= b_e + 1;
315 b_m <= b_m >> 1;
316 b_m[0] <= b_m[0] | b_m[1];
317 end else if ($signed(a_e) < $signed(b_e)) begin
318 a_e <= a_e + 1;
319 a_m <= a_m >> 1;
320 a_m[0] <= a_m[0] | a_m[1];
321 end else begin
322 state <= add_0;
323 end
324 end
325
326 add_0:
327 begin
328 z_e <= a_e;
329 if (a_s == b_s) begin
330 tot <= a_m + b_m;
331 z_s <= a_s;
332 end else begin
333 if (a_m >= b_m) begin
334 tot <= a_m - b_m;
335 z_s <= a_s;
336 end else begin
337 tot <= b_m - a_m;
338 z_s <= b_s;
339 end
340 end
341 state <= add_1;
342 end
343
344 add_1:
345 begin
346 if (tot[27]) begin
347 z_m <= tot[27:4];
348 guard <= tot[3];
349 round_bit <= tot[2];
350 sticky <= tot[1] | tot[0];
351 z_e <= z_e + 1;
352 end else begin
353 z_m <= tot[26:3];
354 guard <= tot[2];
355 round_bit <= tot[1];
356 sticky <= tot[0];
357 end
358 state <= normalise_1;
359 end
360
361 normalise_1:
362 begin
363 if (z_m[23] == 0 && $signed(z_e) > -126) begin
364 z_e <= z_e - 1;
365 z_m <= z_m << 1;
366 z_m[0] <= guard;
367 guard <= round_bit;
368 round_bit <= 0;
369 end else begin
370 state <= normalise_2;
371 end
372 end
373
374 normalise_2:
375 begin
376 if ($signed(z_e) < -126) begin
377 z_e <= z_e + 1;
378 z_m <= z_m >> 1;
379 guard <= z_m[0];
380 round_bit <= guard;
381 sticky <= sticky | round_bit;
382 end else begin
383 state <= round;
384 end
385 end
386
387 round:
388 begin
389 if (guard && (round_bit | sticky | z_m[0])) begin
390 z_m <= z_m + 1;
391 if (z_m == 24'hffffff) begin
392 z_e <=z_e + 1;
393 end
394 end
395 state <= pack;
396 end
397
398 pack:
399 begin
400 z[22 : 0] <= z_m[22:0];
401 z[30 : 23] <= z_e[7:0] + 127;
402 z[31] <= z_s;
403 if ($signed(z_e) == -126 && z_m[23] == 0) begin
404 z[30 : 23] <= 0;
405 end
406 if ($signed(z_e) == -126 && z_m[23:0] == 24'h0) begin
407 z[31] <= 1'b0; // FIX SIGN BUG: -a + a = +0.
408 end
409 //if overflow occurs, return inf
410 if ($signed(z_e) > 127) begin
411 z[22 : 0] <= 0;
412 z[30 : 23] <= 255;
413 z[31] <= z_s;
414 end
415 state <= put_z;
416 end
417
418 put_z:
419 begin
420 s_out_z_stb <= 1;
421 s_out_z <= z;
422 if (s_out_z_stb && out_z_ack) begin
423 s_out_z_stb <= 0;
424 state <= get_a;
425 end
426 end
427
428 endcase
429
430 if (rst == 1) begin
431 state <= get_a;
432 s_in_a_ack <= 0;
433 s_in_b_ack <= 0;
434 s_out_z_stb <= 0;
435 end
436
437 end
438 assign in_a_ack = s_in_a_ack;
439 assign in_b_ack = s_in_b_ack;
440 assign out_z_stb = s_out_z_stb;
441 assign out_z = s_out_z;
442
443 endmodule
444 """
445
446 if __name__ == "__main__":
447 alu = FPADD(width=32)
448 main(alu, ports=[
449 alu.in_a, alu.in_a_stb, alu.in_a_ack,
450 alu.in_b, alu.in_b_stb, alu.in_b_ack,
451 alu.out_z, alu.out_z_stb, alu.out_z_ack,
452 ])