src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
   9
  10
  11 class FPState(FPBase):
  12     def __init__(self, state_from):
  13         self.state_from = state_from
  14
  15     def set_inputs(self, inputs):
  16         self.inputs = inputs
  17         for k,v in inputs.items():
  18             setattr(self, k, v)
  19
  20     def set_outputs(self, outputs):
  21         self.outputs = outputs
  22         for k,v in outputs.items():
  23             setattr(self, k, v)
  24
  25
  26 class FPGetOpA(FPState):
  27
  28     def action(self, m):
  29         self.get_op(m, self.in_a, self.a, "get_b")
  30
  31
  32 class FPGetOpB(FPState):
  33
  34     def action(self, m):
  35         self.get_op(m, self.in_b, self.b, "special_cases")
  36
  37
  38 class FPAddSpecialCases(FPState):
  39
  40     def action(self, m):
  41         s_nomatch = Signal()
  42         m.d.comb += s_nomatch.eq(self.a.s != self.b.s)
  43
  44         m_match = Signal()
  45         m.d.comb += m_match.eq(self.a.m == self.b.m)
  46
  47         # if a is NaN or b is NaN return NaN
  48         with m.If(self.a.is_nan | self.b.is_nan):
  49             m.next = "put_z"
  50             m.d.sync += self.z.nan(1)
  51
  52         # XXX WEIRDNESS for FP16 non-canonical NaN handling
  53         # under review
  54
  55         ## if a is zero and b is NaN return -b
  56         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
  57         #    m.next = "put_z"
  58         #    m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
  59
  60         ## if b is zero and a is NaN return -a
  61         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
  62         #    m.next = "put_z"
  63         #    m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
  64
  65         ## if a is -zero and b is NaN return -b
  66         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
  67         #    m.next = "put_z"
  68         #    m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
  69
  70         ## if b is -zero and a is NaN return -a
  71         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
  72         #    m.next = "put_z"
  73         #    m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
  74
  75         # if a is inf return inf (or NaN)
  76         with m.Elif(self.a.is_inf):
  77             m.next = "put_z"
  78             m.d.sync += self.z.inf(self.a.s)
  79             # if a is inf and signs don't match return NaN
  80             with m.If(self.b.exp_128 & s_nomatch):
  81                 m.d.sync += self.z.nan(1)
  82
  83         # if b is inf return inf
  84         with m.Elif(self.b.is_inf):
  85             m.next = "put_z"
  86             m.d.sync += self.z.inf(self.b.s)
  87
  88         # if a is zero and b zero return signed-a/b
  89         with m.Elif(self.a.is_zero & self.b.is_zero):
  90             m.next = "put_z"
  91             m.d.sync += self.z.create(self.a.s & self.b.s, self.b.e,
  92                                       self.b.m[3:-1])
  93
  94         # if a is zero return b
  95         with m.Elif(self.a.is_zero):
  96             m.next = "put_z"
  97             m.d.sync += self.z.create(self.b.s, self.b.e, self.b.m[3:-1])
  98
  99         # if b is zero return a
 100         with m.Elif(self.b.is_zero):
 101             m.next = "put_z"
 102             m.d.sync += self.z.create(self.a.s, self.a.e, self.a.m[3:-1])
 103
 104         # if a equal to -b return zero (+ve zero)
 105         with m.Elif(s_nomatch & m_match & (self.a.e == self.b.e)):
 106             m.next = "put_z"
 107             m.d.sync += self.z.zero(0)
 108
 109         # Denormalised Number checks
 110         with m.Else():
 111             m.next = "denormalise"
 112
 113
 114 class FPAddDeNorm(FPState):
 115
 116     def action(self, m):
 117         # Denormalised Number checks
 118         m.next = "align"
 119         self.denormalise(m, self.a)
 120         self.denormalise(m, self.b)
 121
 122 class FPAddAlignMulti(FPState):
 123
 124     def action(self, m):
 125         # NOTE: this does *not* do single-cycle multi-shifting,
 126         #       it *STAYS* in the align state until exponents match
 127
 128         # exponent of a greater than b: shift b down
 129         with m.If(self.a.e > self.b.e):
 130             m.d.sync += self.b.shift_down()
 131         # exponent of b greater than a: shift a down
 132         with m.Elif(self.a.e < self.b.e):
 133             m.d.sync += self.a.shift_down()
 134         # exponents equal: move to next stage.
 135         with m.Else():
 136             m.next = "add_0"
 137
 138
 139 class FPAddAlignSingle(FPState):
 140
 141     def action(self, m):
 142         # This one however (single-cycle) will do the shift
 143         # in one go.
 144
 145         # XXX TODO: the shifter used here is quite expensive
 146         # having only one would be better
 147
 148         ediff = Signal((len(self.a.e), True), reset_less=True)
 149         ediffr = Signal((len(self.a.e), True), reset_less=True)
 150         m.d.comb += ediff.eq(self.a.e - self.b.e)
 151         m.d.comb += ediffr.eq(self.b.e - self.a.e)
 152         with m.If(ediff > 0):
 153             m.d.sync += self.b.shift_down_multi(ediff)
 154         # exponent of b greater than a: shift a down
 155         with m.Elif(ediff < 0):
 156             m.d.sync += self.a.shift_down_multi(ediffr)
 157
 158         m.next = "add_0"
 159
 160
 161 class FPADD(FPBase):
 162
 163     def __init__(self, width, single_cycle=False):
 164         FPBase.__init__(self)
 165         self.width = width
 166         self.single_cycle = single_cycle
 167
 168         self.in_a  = FPOp(width)
 169         self.in_b  = FPOp(width)
 170         self.out_z = FPOp(width)
 171
 172     def get_fragment(self, platform=None):
 173         """ creates the HDL code-fragment for FPAdd
 174         """
 175         m = Module()
 176
 177         # Latches
 178         a = FPNumIn(self.in_a, self.width)
 179         b = FPNumIn(self.in_b, self.width)
 180         z = FPNumOut(self.width, False)
 181
 182         m.submodules.fpnum_a = a
 183         m.submodules.fpnum_b = b
 184         m.submodules.fpnum_z = z
 185
 186         w = z.m_width + 4
 187         tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow
 188
 189         of = Overflow()
 190         m.submodules.overflow = of
 191
 192         geta = FPGetOpA("get_a")
 193         geta.set_inputs({"in_a": self.in_a})
 194         geta.set_outputs({"a": a})
 195         m.d.comb += a.v.eq(self.in_a.v) # links in_a to a
 196
 197         getb = FPGetOpB("get_b")
 198         getb.set_inputs({"in_b": self.in_b})
 199         getb.set_outputs({"b": b})
 200         m.d.comb += b.v.eq(self.in_b.v) # links in_b to b
 201
 202         sc = FPAddSpecialCases("special_cases")
 203         sc.set_inputs({"a": a, "b": b})
 204         sc.set_outputs({"z": z})
 205
 206         dn = FPAddDeNorm("denormalise")
 207         dn.set_inputs({"a": a, "b": b})
 208         dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 209
 210         if self.single_cycle:
 211             alm = FPAddAlignSingle("align")
 212         else:
 213             alm = FPAddAlignMulti("align")
 214         alm.set_inputs({"a": a, "b": b})
 215         alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 216
 217         with m.FSM() as fsm:
 218
 219             # ******
 220             # gets operand a
 221
 222             with m.State("get_a"):
 223                 geta.action(m)
 224
 225             # ******
 226             # gets operand b
 227
 228             with m.State("get_b"):
 229                 #self.get_op(m, self.in_b, b, "special_cases")
 230                 getb.action(m)
 231
 232             # ******
 233             # special cases: NaNs, infs, zeros, denormalised
 234             # NOTE: some of these are unique to add.  see "Special Operations"
 235             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 236
 237             with m.State("special_cases"):
 238                 sc.action(m)
 239
 240             # ******
 241             # denormalise.
 242
 243             with m.State("denormalise"):
 244                 dn.action(m)
 245
 246             # ******
 247             # align.
 248
 249             with m.State("align"):
 250                 alm.action(m)
 251
 252             # ******
 253             # First stage of add.  covers same-sign (add) and subtract
 254             # special-casing when mantissas are greater or equal, to
 255             # give greatest accuracy.
 256
 257             with m.State("add_0"):
 258                 m.next = "add_1"
 259                 m.d.sync += z.e.eq(a.e)
 260                 # same-sign (both negative or both positive) add mantissas
 261                 with m.If(a.s == b.s):
 262                     m.d.sync += [
 263                         tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
 264                         z.s.eq(a.s)
 265                     ]
 266                 # a mantissa greater than b, use a
 267                 with m.Elif(a.m >= b.m):
 268                     m.d.sync += [
 269                         tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
 270                         z.s.eq(a.s)
 271                     ]
 272                 # b mantissa greater than a, use b
 273                 with m.Else():
 274                     m.d.sync += [
 275                         tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
 276                         z.s.eq(b.s)
 277                 ]
 278
 279             # ******
 280             # Second stage of add: preparation for normalisation.
 281             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 282
 283             with m.State("add_1"):
 284                 m.next = "normalise_1"
 285                 # tot[27] gets set when the sum overflows. shift result down
 286                 with m.If(tot[-1]):
 287                     m.d.sync += [
 288                         z.m.eq(tot[4:]),
 289                         of.m0.eq(tot[4]),
 290                         of.guard.eq(tot[3]),
 291                         of.round_bit.eq(tot[2]),
 292                         of.sticky.eq(tot[1] | tot[0]),
 293                         z.e.eq(z.e + 1)
 294                 ]
 295                 # tot[27] zero case
 296                 with m.Else():
 297                     m.d.sync += [
 298                         z.m.eq(tot[3:]),
 299                         of.m0.eq(tot[3]),
 300                         of.guard.eq(tot[2]),
 301                         of.round_bit.eq(tot[1]),
 302                         of.sticky.eq(tot[0])
 303                 ]
 304
 305             # ******
 306             # First stage of normalisation.
 307
 308             with m.State("normalise_1"):
 309                 self.normalise_1(m, z, of, "normalise_2")
 310
 311             # ******
 312             # Second stage of normalisation.
 313
 314             with m.State("normalise_2"):
 315                 self.normalise_2(m, z, of, "round")
 316
 317             # ******
 318             # rounding stage
 319
 320             with m.State("round"):
 321                 self.roundz(m, z, of, "corrections")
 322
 323             # ******
 324             # correction stage
 325
 326             with m.State("corrections"):
 327                 self.corrections(m, z, "pack")
 328
 329             # ******
 330             # pack stage
 331
 332             with m.State("pack"):
 333                 self.pack(m, z, "put_z")
 334
 335             # ******
 336             # put_z stage
 337
 338             with m.State("put_z"):
 339                 self.put_z(m, z, self.out_z, "get_a")
 340
 341         return m
 342
 343
 344 if __name__ == "__main__":
 345     alu = FPADD(width=32)
 346     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 347
 348
 349     # works... but don't use, just do "python fname.py convert -t v"
 350     #print (verilog.convert(alu, ports=[
 351     #                        ports=alu.in_a.ports() + \
 352     #                              alu.in_b.ports() + \
 353     #                              alu.out_z.ports())