1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
6 from nmigen
.cli
import main
, verilog
8 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
11 class FPState(FPBase
):
12 def __init__(self
, state_from
):
13 self
.state_from
= state_from
15 def set_inputs(self
, inputs
):
17 for k
,v
in inputs
.items():
20 def set_outputs(self
, outputs
):
21 self
.outputs
= outputs
22 for k
,v
in outputs
.items():
26 class FPGetOpA(FPState
):
31 self
.get_op(m
, self
.in_a
, self
.a
, "get_b")
34 class FPGetOpB(FPState
):
39 self
.get_op(m
, self
.in_b
, self
.b
, "special_cases")
42 class FPAddSpecialCases(FPState
):
43 """ special cases: NaNs, infs, zeros, denormalised
44 NOTE: some of these are unique to add. see "Special Operations"
45 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
50 m
.d
.comb
+= s_nomatch
.eq(self
.a
.s
!= self
.b
.s
)
53 m
.d
.comb
+= m_match
.eq(self
.a
.m
== self
.b
.m
)
55 # if a is NaN or b is NaN return NaN
56 with m
.If(self
.a
.is_nan | self
.b
.is_nan
):
58 m
.d
.sync
+= self
.z
.nan(1)
60 # XXX WEIRDNESS for FP16 non-canonical NaN handling
63 ## if a is zero and b is NaN return -b
64 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
66 # m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
68 ## if b is zero and a is NaN return -a
69 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
71 # m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
73 ## if a is -zero and b is NaN return -b
74 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
76 # m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
78 ## if b is -zero and a is NaN return -a
79 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
81 # m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
83 # if a is inf return inf (or NaN)
84 with m
.Elif(self
.a
.is_inf
):
86 m
.d
.sync
+= self
.z
.inf(self
.a
.s
)
87 # if a is inf and signs don't match return NaN
88 with m
.If(self
.b
.exp_128
& s_nomatch
):
89 m
.d
.sync
+= self
.z
.nan(1)
91 # if b is inf return inf
92 with m
.Elif(self
.b
.is_inf
):
94 m
.d
.sync
+= self
.z
.inf(self
.b
.s
)
96 # if a is zero and b zero return signed-a/b
97 with m
.Elif(self
.a
.is_zero
& self
.b
.is_zero
):
99 m
.d
.sync
+= self
.z
.create(self
.a
.s
& self
.b
.s
, self
.b
.e
,
102 # if a is zero return b
103 with m
.Elif(self
.a
.is_zero
):
105 m
.d
.sync
+= self
.z
.create(self
.b
.s
, self
.b
.e
, self
.b
.m
[3:-1])
107 # if b is zero return a
108 with m
.Elif(self
.b
.is_zero
):
110 m
.d
.sync
+= self
.z
.create(self
.a
.s
, self
.a
.e
, self
.a
.m
[3:-1])
112 # if a equal to -b return zero (+ve zero)
113 with m
.Elif(s_nomatch
& m_match
& (self
.a
.e
== self
.b
.e
)):
115 m
.d
.sync
+= self
.z
.zero(0)
117 # Denormalised Number checks
119 m
.next
= "denormalise"
122 class FPAddDeNorm(FPState
):
125 # Denormalised Number checks
127 self
.denormalise(m
, self
.a
)
128 self
.denormalise(m
, self
.b
)
131 class FPAddAlignMulti(FPState
):
134 # NOTE: this does *not* do single-cycle multi-shifting,
135 # it *STAYS* in the align state until exponents match
137 # exponent of a greater than b: shift b down
138 with m
.If(self
.a
.e
> self
.b
.e
):
139 m
.d
.sync
+= self
.b
.shift_down()
140 # exponent of b greater than a: shift a down
141 with m
.Elif(self
.a
.e
< self
.b
.e
):
142 m
.d
.sync
+= self
.a
.shift_down()
143 # exponents equal: move to next stage.
148 class FPAddAlignSingle(FPState
):
151 # This one however (single-cycle) will do the shift
154 # XXX TODO: the shifter used here is quite expensive
155 # having only one would be better
157 ediff
= Signal((len(self
.a
.e
), True), reset_less
=True)
158 ediffr
= Signal((len(self
.a
.e
), True), reset_less
=True)
159 m
.d
.comb
+= ediff
.eq(self
.a
.e
- self
.b
.e
)
160 m
.d
.comb
+= ediffr
.eq(self
.b
.e
- self
.a
.e
)
161 with m
.If(ediff
> 0):
162 m
.d
.sync
+= self
.b
.shift_down_multi(ediff
)
163 # exponent of b greater than a: shift a down
164 with m
.Elif(ediff
< 0):
165 m
.d
.sync
+= self
.a
.shift_down_multi(ediffr
)
170 class FPAddStage0(FPState
):
171 """ First stage of add. covers same-sign (add) and subtract
172 special-casing when mantissas are greater or equal, to
173 give greatest accuracy.
178 m
.d
.sync
+= self
.z
.e
.eq(self
.a
.e
)
179 # same-sign (both negative or both positive) add mantissas
180 with m
.If(self
.a
.s
== self
.b
.s
):
182 self
.tot
.eq(Cat(self
.a
.m
, 0) + Cat(self
.b
.m
, 0)),
183 self
.z
.s
.eq(self
.a
.s
)
185 # a mantissa greater than b, use a
186 with m
.Elif(self
.a
.m
>= self
.b
.m
):
188 self
.tot
.eq(Cat(self
.a
.m
, 0) - Cat(self
.b
.m
, 0)),
189 self
.z
.s
.eq(self
.a
.s
)
191 # b mantissa greater than a, use b
194 self
.tot
.eq(Cat(self
.b
.m
, 0) - Cat(self
.a
.m
, 0)),
195 self
.z
.s
.eq(self
.b
.s
)
199 class FPAddStage1(FPState
):
200 """ Second stage of add: preparation for normalisation.
201 detects when tot sum is too big (tot[27] is kinda a carry bit)
205 m
.next
= "normalise_1"
206 # tot[27] gets set when the sum overflows. shift result down
207 with m
.If(self
.tot
[-1]):
209 self
.z
.m
.eq(self
.tot
[4:]),
210 self
.of
.m0
.eq(self
.tot
[4]),
211 self
.of
.guard
.eq(self
.tot
[3]),
212 self
.of
.round_bit
.eq(self
.tot
[2]),
213 self
.of
.sticky
.eq(self
.tot
[1] | self
.tot
[0]),
214 self
.z
.e
.eq(self
.z
.e
+ 1)
219 self
.z
.m
.eq(self
.tot
[3:]),
220 self
.of
.m0
.eq(self
.tot
[3]),
221 self
.of
.guard
.eq(self
.tot
[2]),
222 self
.of
.round_bit
.eq(self
.tot
[1]),
223 self
.of
.sticky
.eq(self
.tot
[0])
227 class FPNorm1(FPState
):
230 self
.normalise_1(m
, self
.z
, self
.of
, "normalise_2")
233 class FPNorm2(FPState
):
236 self
.normalise_2(m
, self
.z
, self
.of
, "round")
239 class FPRound(FPState
):
242 self
.roundz(m
, self
.z
, self
.of
, "corrections")
245 class FPCorrections(FPState
):
248 self
.corrections(m
, self
.z
, "pack")
251 class FPPack(FPState
):
254 self
.pack(m
, self
.z
, "put_z")
257 class FPPutZ(FPState
):
260 self
.put_z(m
, self
.z
, self
.out_z
, "get_a")
265 def __init__(self
, width
, single_cycle
=False):
266 FPBase
.__init
__(self
)
268 self
.single_cycle
= single_cycle
270 self
.in_a
= FPOp(width
)
271 self
.in_b
= FPOp(width
)
272 self
.out_z
= FPOp(width
)
276 def add_state(self
, state
):
277 self
.states
.append(state
)
280 def get_fragment(self
, platform
=None):
281 """ creates the HDL code-fragment for FPAdd
286 a
= FPNumIn(self
.in_a
, self
.width
)
287 b
= FPNumIn(self
.in_b
, self
.width
)
288 z
= FPNumOut(self
.width
, False)
290 m
.submodules
.fpnum_a
= a
291 m
.submodules
.fpnum_b
= b
292 m
.submodules
.fpnum_z
= z
295 tot
= Signal(w
, reset_less
=True) # sticky/round/guard, {mantissa} result, 1 overflow
298 m
.submodules
.overflow
= of
300 geta
= self
.add_state(FPGetOpA("get_a"))
301 geta
.set_inputs({"in_a": self
.in_a
})
302 geta
.set_outputs({"a": a
})
303 m
.d
.comb
+= a
.v
.eq(self
.in_a
.v
) # links in_a to a
305 getb
= self
.add_state(FPGetOpB("get_b"))
306 getb
.set_inputs({"in_b": self
.in_b
})
307 getb
.set_outputs({"b": b
})
308 m
.d
.comb
+= b
.v
.eq(self
.in_b
.v
) # links in_b to b
310 sc
= self
.add_state(FPAddSpecialCases("special_cases"))
311 sc
.set_inputs({"a": a
, "b": b
})
312 sc
.set_outputs({"z": z
})
314 dn
= self
.add_state(FPAddDeNorm("denormalise"))
315 dn
.set_inputs({"a": a
, "b": b
})
316 dn
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
318 if self
.single_cycle
:
319 alm
= self
.add_state(FPAddAlignSingle("align"))
321 alm
= self
.add_state(FPAddAlignMulti("align"))
322 alm
.set_inputs({"a": a
, "b": b
})
323 alm
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
325 add0
= self
.add_state(FPAddStage0("add_0"))
326 add0
.set_inputs({"a": a
, "b": b
})
327 add0
.set_outputs({"z": z
, "tot": tot
})
329 add1
= self
.add_state(FPAddStage1("add_1"))
330 add1
.set_inputs({"tot": tot
, "z": z
}) # Z input passes through
331 add1
.set_outputs({"z": z
, "of": of
}) # XXX Z as output
333 n1
= self
.add_state(FPNorm1("normalise_1"))
334 n1
.set_inputs({"z": z
, "of": of
}) # XXX Z as output
335 n1
.set_outputs({"z": z
}) # XXX Z as output
337 n2
= self
.add_state(FPNorm2("normalise_2"))
338 n2
.set_inputs({"z": z
, "of": of
}) # XXX Z as output
339 n2
.set_outputs({"z": z
}) # XXX Z as output
341 rn
= self
.add_state(FPRound("round"))
342 rn
.set_inputs({"z": z
, "of": of
}) # XXX Z as output
343 rn
.set_outputs({"z": z
}) # XXX Z as output
345 cor
= self
.add_state(FPCorrections("corrections"))
346 cor
.set_inputs({"z": z
}) # XXX Z as output
347 cor
.set_outputs({"z": z
}) # XXX Z as output
349 pa
= self
.add_state(FPPack("pack"))
350 pa
.set_inputs({"z": z
}) # XXX Z as output
351 pa
.set_outputs({"z": z
}) # XXX Z as output
353 pz
= self
.add_state(FPPutZ("put_z"))
354 pz
.set_inputs({"z": z
})
355 pz
.set_outputs({"out_z": self
.out_z
})
359 for state
in self
.states
:
360 with m
.State(state
.state_from
):
366 if __name__
== "__main__":
367 alu
= FPADD(width
=32)
368 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
371 # works... but don't use, just do "python fname.py convert -t v"
372 #print (verilog.convert(alu, ports=[
373 # ports=alu.in_a.ports() + \
374 # alu.in_b.ports() + \