1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
6 from nmigen
.cli
import main
9 def __init__(self
, width
, m_width
=None):
13 self
.v
= Signal(width
) # Latched copy of value
14 self
.m
= Signal(m_width
) # Mantissa: ??? seems to be 1 bit extra??
15 self
.e
= Signal((10, True)) # Exponent: 10 bits, signed
16 self
.s
= Signal() # Sign bit
20 return [self
.m
.eq(Cat(0, 0, 0, v
[0:23])), # mantissa
21 self
.e
.eq(Cat(v
[23:31]) - 127), # exponent (take off bias)
22 self
.s
.eq(Cat(v
[31])), # sign
25 def create(self
, s
, e
, m
):
27 self
.v
[31].eq(s
), # sign
28 self
.v
[23:31].eq(e
), # exp
29 self
.v
[0:23].eq(m
) # mantissa
33 return self
.create(s
, 0xff, 1<<22)
36 return self
.create(s
, 0xff, 0)
40 def __init__(self
, width
):
43 self
.in_a
= Signal(width
)
44 self
.in_a_stb
= Signal()
45 self
.in_a_ack
= Signal()
47 self
.in_b
= Signal(width
)
48 self
.in_b_stb
= Signal()
49 self
.in_b_ack
= Signal()
51 self
.out_z
= Signal(width
)
52 self
.out_z_stb
= Signal()
53 self
.out_z_ack
= Signal()
55 s_out_z_stb
= Signal()
56 s_out_z
= Signal(width
)
60 def get_fragment(self
, platform
):
66 z
= FPNum(self
.width
, 24)
84 with m
.State("get_a"):
85 with m
.If((self
.in_a_ack
) & (self
.in_a_stb
)):
92 m
.d
.sync
+= self
.in_a_ack
.eq(1)
97 with m
.State("get_b"):
98 with m
.If((self
.in_b_ack
) & (self
.in_b_stb
)):
105 m
.d
.sync
+= self
.in_b_ack
.eq(1)
108 # unpacks operands into sign, mantissa and exponent
110 with m
.State("unpack"):
111 m
.next
= "special_cases"
112 m
.d
.sync
+= a
.decode()
113 m
.d
.sync
+= b
.decode()
116 # special cases: NaNs, infs, zeros, denormalised
118 with m
.State("special_cases"):
120 # if a is NaN or b is NaN return NaN
121 with m
.If(((a
.e
== 128) & (a
.m
!= 0)) | \
122 ((b
.e
== 128) & (b
.m
!= 0))):
126 # if a is inf return inf (or NaN)
127 with m
.Elif(a
.e
== 128):
129 m
.d
.sync
+= z
.inf(a
.s
)
130 # if a is inf and signs don't match return NaN
131 with m
.If((b
.e
== 128) & (a
.s
!= b
.s
)):
132 m
.d
.sync
+= z
.nan(b
.s
)
134 # if b is inf return inf
135 with m
.Elif(b
.e
== 128):
137 m
.d
.sync
+= z
.inf(b
.s
)
139 # if a is zero and b zero return signed-a/b
140 with m
.Elif(((a
.e
== -127) & (a
.m
== 0)) & \
141 ((b
.e
== -127) & (b
.m
== 0))):
143 m
.d
.sync
+= z
.create(a
.s
& b
.s
, b
.e
[0:8] + 127, b
.m
[3:26])
145 # if a is zero return b
146 with m
.Elif((a
.e
== -127) & (a
.m
== 0)):
148 m
.d
.sync
+= z
.create(b
.s
, b
.e
[0:8] + 127, b
.m
[3:26])
150 # if b is zero return a
151 with m
.Elif((b
.e
== -127) & (b
.m
== 0)):
153 m
.d
.sync
+= z
.create(a
.s
, a
.e
[0:8] + 127, a
.m
[3:26])
155 # Denormalised Number checks
158 # denormalise a check
159 with m
.If(a
.e
== -127):
160 m
.d
.sync
+= a
.e
.eq(-126) # limit a exponent
162 m
.d
.sync
+= a
.m
[26].eq(1) # set highest mantissa bit
163 # denormalise b check
164 with m
.If(b
.e
== -127):
165 m
.d
.sync
+= b
.e
.eq(-126) # limit b exponent
167 m
.d
.sync
+= b
.m
[26].eq(1) # set highest mantissa bit
170 # align. NOTE: this does *not* do single-cycle multi-shifting,
171 # it *STAYS* in the align state until the exponents match
173 with m
.State("align"):
174 # exponent of a greater than b: increment b exp, shift b mant
175 with m
.If(a
.e
> b
.e
):
179 b
.m
[0].eq(b
.m
[0] | b
.m
[1]) # moo??
181 # exponent of b greater than a: increment a exp, shift a mant
182 with m
.Elif(a
.e
< b
.e
):
186 a
.m
[0].eq(a
.m
[0] | a
.m
[1]) # moo??
188 # exponents equal: move to next stage.
193 # First stage of add. covers same-sign (add) and subtract
194 # special-casing when mantissas are greater or equal, to
195 # give greatest accuracy.
197 with m
.State("add_0"):
199 m
.d
.sync
+= z
.e
.eq(a
.e
)
200 # same-sign (both negative or both positive) add mantissas
201 with m
.If(a
.s
== b
.s
):
206 # a mantissa greater than b, use a
207 with m
.Elif(a
.m
>= b
.m
):
212 # b mantissa greater than a, use b
220 # Second stage of add: preparation for normalisation.
221 # detects when tot sum is too big (tot[27] is kinda a carry bit)
223 with m
.State("add_1"):
224 m
.next
= "normalise_1"
225 # tot[27] gets set when the sum overflows. shift result down
230 round_bit
.eq(tot
[2]),
231 sticky
.eq(tot
[1] | tot
[0]),
239 round_bit
.eq(tot
[1]),
244 # First stage of normalisation.
245 # NOTE: just like "align", this one keeps going round every clock
246 # until the result's exponent is within acceptable "range"
247 # NOTE: the weirdness of reassigning guard and round is due to
248 # the extra mantissa bits coming from tot[0..2]
250 with m
.State("normalise_1"):
251 with m
.If((z
.m
[23] == 0) & (z
.e
> -126)):
253 z
.e
.eq(z
.e
- 1), # DECREASE exponent
254 z
.m
.eq(z
.m
<< 1), # shift mantissa UP
255 z
.m
[0].eq(guard
), # steal guard bit (was tot[2])
256 guard
.eq(round_bit
), # steal round_bit (was tot[1])
259 m
.next
= "normalize_2"
262 # Second stage of normalisation.
263 # NOTE: just like "align", this one keeps going round every clock
264 # until the result's exponent is within acceptable "range"
265 # NOTE: the weirdness of reassigning guard and round is due to
266 # the extra mantissa bits coming from tot[0..2]
268 with m
.State("normalise_2"):
269 with m
.If(z
.e
< -126):
271 z
.e
.eq(z
.e
+ 1), # INCREASE exponent
272 z
.m
.eq(z
.m
>> 1), # shift mantissa DOWN
275 sticky
.eq(sticky | round_bit
)
283 with m
.State("round"):
285 with m
.If(guard
& (round_bit | sticky | z
.m
[0])):
286 m
.d
.sync
+= z
.m
.eq(z
.m
+ 1) # mantissa rounds up
287 with m
.If(z
.m
== 0xffffff): # all 1s
288 m
.d
.sync
+= z
.e
.eq(z
.e
+ 1) # exponent rounds up
293 always @(posedge clk)
301 if (s_in_a_ack && in_a_stb) begin
311 if (s_in_b_ack && in_b_stb) begin
320 a_m <= {a[22 : 0], 3'd0};
321 b_m <= {b[22 : 0], 3'd0};
322 a_e <= a[30 : 23] - 127;
323 b_e <= b[30 : 23] - 127;
326 state <= special_cases;
331 //if a is NaN or b is NaN return NaN
332 if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
338 //if a is inf return inf
339 end else if (a_e == 128) begin
343 //if a is inf and signs don't match return nan
344 if ((b_e == 128) && (a_s != b_s)) begin
351 //if b is inf return inf
352 end else if (b_e == 128) begin
357 //if a is zero return b
358 end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
360 z[30:23] <= b_e[7:0] + 127;
361 z[22:0] <= b_m[26:3];
363 //if a is zero return b
364 end else if (($signed(a_e) == -127) && (a_m == 0)) begin
366 z[30:23] <= b_e[7:0] + 127;
367 z[22:0] <= b_m[26:3];
369 //if b is zero return a
370 end else if (($signed(b_e) == -127) && (b_m == 0)) begin
372 z[30:23] <= a_e[7:0] + 127;
373 z[22:0] <= a_m[26:3];
376 //Denormalised Number
377 if ($signed(a_e) == -127) begin
382 //Denormalised Number
383 if ($signed(b_e) == -127) begin
394 if ($signed(a_e) > $signed(b_e)) begin
397 b_m[0] <= b_m[0] | b_m[1];
398 end else if ($signed(a_e) < $signed(b_e)) begin
401 a_m[0] <= a_m[0] | a_m[1];
410 if (a_s == b_s) begin
414 if (a_m >= b_m) begin
431 sticky <= tot[1] | tot[0];
439 state <= normalise_1;
444 if (z_m[23] == 0 && $signed(z_e) > -126) begin
451 state <= normalise_2;
457 if ($signed(z_e) < -126) begin
462 sticky <= sticky | round_bit;
470 if (guard && (round_bit | sticky | z_m[0])) begin
472 if (z_m == 24'hffffff) begin
481 z[22 : 0] <= z_m[22:0];
482 z[30 : 23] <= z_e[7:0] + 127;
484 if ($signed(z_e) == -126 && z_m[23] == 0) begin
487 if ($signed(z_e) == -126 && z_m[23:0] == 24'h0) begin
488 z[31] <= 1'b0; // FIX SIGN BUG: -a + a = +0.
490 //if overflow occurs, return inf
491 if ($signed(z_e) > 127) begin
503 if (s_out_z_stb && out_z_ack) begin
519 assign in_a_ack = s_in_a_ack;
520 assign in_b_ack = s_in_b_ack;
521 assign out_z_stb = s_out_z_stb;
522 assign out_z = s_out_z;
527 if __name__
== "__main__":
528 alu
= FPADD(width
=32)
530 alu
.in_a
, alu
.in_a_stb
, alu
.in_a_ack
,
531 alu
.in_b
, alu
.in_b_stb
, alu
.in_b_ack
,
532 alu
.out_z
, alu
.out_z_stb
, alu
.out_z_ack
,