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[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width, id_wid):
189 Trigger.__init__(self)
190 self.width = width
191 self.id_wid = id_wid
192 self.in_op1 = Signal(width, reset_less=True)
193 self.in_op2 = Signal(width, reset_less=True)
194 self.o = FPNumBase2Ops(width, id_wid)
195
196 def ospec(self):
197 return FPNumBase2Ops(self.width, self.id_wid)
198
199 def elaborate(self, platform):
200 m = Trigger.elaborate(self, platform)
201 #m.submodules.get_op_in = self.in_op
202 m.submodules.get_op1_out = self.o.a
203 m.submodules.get_op2_out = self.o.b
204 out_op1 = FPNumIn(None, self.width)
205 out_op2 = FPNumIn(None, self.width)
206 with m.If(self.trigger):
207 m.d.comb += [
208 out_op1.decode(self.in_op1),
209 out_op2.decode(self.in_op2),
210 self.o.a.eq(out_op1),
211 self.o.b.eq(out_op2),
212 ]
213 return m
214
215
216 class FPGet2Op(FPState):
217 """ gets operands
218 """
219
220 def __init__(self, in_state, out_state, in_op1, in_op2, width, id_wid):
221 FPState.__init__(self, in_state)
222 self.out_state = out_state
223 self.mod = FPGet2OpMod(width, id_wid)
224 self.in_op1 = in_op1
225 self.in_op2 = in_op2
226 self.o = self.mod.ospec()
227 self.in_stb = Signal(reset_less=True)
228 self.out_ack = Signal(reset_less=True)
229 self.out_decode = Signal(reset_less=True)
230
231 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
232 """ links module to inputs and outputs
233 """
234 m.submodules.get_ops = self.mod
235 m.d.comb += self.mod.in_op1.eq(in_op1)
236 m.d.comb += self.mod.in_op2.eq(in_op2)
237 m.d.comb += self.mod.stb.eq(in_stb)
238 m.d.comb += self.out_ack.eq(self.mod.ack)
239 m.d.comb += self.out_decode.eq(self.mod.trigger)
240 m.d.comb += in_ack.eq(self.mod.ack)
241
242 def action(self, m):
243 with m.If(self.out_decode):
244 m.next = self.out_state
245 m.d.sync += [
246 self.mod.ack.eq(0),
247 self.o.eq(self.mod.o),
248 ]
249 with m.Else():
250 m.d.sync += self.mod.ack.eq(1)
251
252
253 class FPNumBase2Ops:
254
255 def __init__(self, width, id_wid, m_extra=True):
256 self.a = FPNumBase(width, m_extra)
257 self.b = FPNumBase(width, m_extra)
258 self.mid = Signal(id_wid, reset_less=True)
259
260 def eq(self, i):
261 return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
262
263
264 class FPAddSpecialCasesMod:
265 """ special cases: NaNs, infs, zeros, denormalised
266 NOTE: some of these are unique to add. see "Special Operations"
267 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
268 """
269
270 def __init__(self, width, id_wid):
271 self.width = width
272 self.id_wid = id_wid
273 self.i = self.ispec()
274 self.o = self.ospec()
275 self.out_do_z = Signal(reset_less=True)
276
277 def ispec(self):
278 return FPNumBase2Ops(self.width, self.id_wid)
279
280 def ospec(self):
281 return FPPackData(self.width, self.id_wid)
282
283 def setup(self, m, in_a, in_b, out_do_z):
284 """ links module to inputs and outputs
285 """
286 m.submodules.specialcases = self
287 m.d.comb += self.i.a.eq(in_a)
288 m.d.comb += self.i.b.eq(in_b)
289 m.d.comb += out_do_z.eq(self.out_do_z)
290
291 def elaborate(self, platform):
292 m = Module()
293
294 m.submodules.sc_in_a = self.i.a
295 m.submodules.sc_in_b = self.i.b
296 m.submodules.sc_out_z = self.o.z
297
298 s_nomatch = Signal()
299 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
300
301 m_match = Signal()
302 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
303
304 # if a is NaN or b is NaN return NaN
305 with m.If(self.i.a.is_nan | self.i.b.is_nan):
306 m.d.comb += self.out_do_z.eq(1)
307 m.d.comb += self.o.z.nan(0)
308
309 # XXX WEIRDNESS for FP16 non-canonical NaN handling
310 # under review
311
312 ## if a is zero and b is NaN return -b
313 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
314 # m.d.comb += self.out_do_z.eq(1)
315 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
316
317 ## if b is zero and a is NaN return -a
318 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
319 # m.d.comb += self.out_do_z.eq(1)
320 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
321
322 ## if a is -zero and b is NaN return -b
323 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
324 # m.d.comb += self.out_do_z.eq(1)
325 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
326
327 ## if b is -zero and a is NaN return -a
328 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
329 # m.d.comb += self.out_do_z.eq(1)
330 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
331
332 # if a is inf return inf (or NaN)
333 with m.Elif(self.i.a.is_inf):
334 m.d.comb += self.out_do_z.eq(1)
335 m.d.comb += self.o.z.inf(self.i.a.s)
336 # if a is inf and signs don't match return NaN
337 with m.If(self.i.b.exp_128 & s_nomatch):
338 m.d.comb += self.o.z.nan(0)
339
340 # if b is inf return inf
341 with m.Elif(self.i.b.is_inf):
342 m.d.comb += self.out_do_z.eq(1)
343 m.d.comb += self.o.z.inf(self.i.b.s)
344
345 # if a is zero and b zero return signed-a/b
346 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
349 self.i.b.e,
350 self.i.b.m[3:-1])
351
352 # if a is zero return b
353 with m.Elif(self.i.a.is_zero):
354 m.d.comb += self.out_do_z.eq(1)
355 m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
356 self.i.b.m[3:-1])
357
358 # if b is zero return a
359 with m.Elif(self.i.b.is_zero):
360 m.d.comb += self.out_do_z.eq(1)
361 m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
362 self.i.a.m[3:-1])
363
364 # if a equal to -b return zero (+ve zero)
365 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
366 m.d.comb += self.out_do_z.eq(1)
367 m.d.comb += self.o.z.zero(0)
368
369 # Denormalised Number checks
370 with m.Else():
371 m.d.comb += self.out_do_z.eq(0)
372
373 return m
374
375
376 class FPID:
377 def __init__(self, id_wid):
378 self.id_wid = id_wid
379 if self.id_wid:
380 self.in_mid = Signal(id_wid, reset_less=True)
381 self.out_mid = Signal(id_wid, reset_less=True)
382 else:
383 self.in_mid = None
384 self.out_mid = None
385
386 def idsync(self, m):
387 if self.id_wid is not None:
388 m.d.sync += self.out_mid.eq(self.in_mid)
389
390
391 class FPAddSpecialCases(FPState, FPID):
392 """ special cases: NaNs, infs, zeros, denormalised
393 NOTE: some of these are unique to add. see "Special Operations"
394 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
395 """
396
397 def __init__(self, width, id_wid):
398 FPState.__init__(self, "special_cases")
399 FPID.__init__(self, id_wid)
400 self.mod = FPAddSpecialCasesMod(width)
401 self.out_z = self.mod.ospec()
402 self.out_do_z = Signal(reset_less=True)
403
404 def setup(self, m, in_a, in_b, in_mid):
405 """ links module to inputs and outputs
406 """
407 self.mod.setup(m, in_a, in_b, self.out_do_z)
408 if self.in_mid is not None:
409 m.d.comb += self.in_mid.eq(in_mid)
410
411 def action(self, m):
412 self.idsync(m)
413 with m.If(self.out_do_z):
414 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
415 m.next = "put_z"
416 with m.Else():
417 m.next = "denormalise"
418
419
420 class FPAddSpecialCasesDeNorm(FPState, FPID):
421 """ special cases: NaNs, infs, zeros, denormalised
422 NOTE: some of these are unique to add. see "Special Operations"
423 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
424 """
425
426 def __init__(self, width, id_wid):
427 FPState.__init__(self, "special_cases")
428 FPID.__init__(self, id_wid)
429 self.smod = FPAddSpecialCasesMod(width, id_wid)
430 self.out_z = self.smod.ospec()
431 self.out_do_z = Signal(reset_less=True)
432
433 self.dmod = FPAddDeNormMod(width, id_wid)
434 self.o = self.dmod.ospec()
435
436 def setup(self, m, in_a, in_b, in_mid):
437 """ links module to inputs and outputs
438 """
439 self.smod.setup(m, in_a, in_b, self.out_do_z)
440 self.dmod.setup(m, in_a, in_b)
441 if self.in_mid is not None:
442 m.d.comb += self.in_mid.eq(in_mid)
443
444 def action(self, m):
445 self.idsync(m)
446 with m.If(self.out_do_z):
447 m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
448 m.next = "put_z"
449 with m.Else():
450 m.next = "align"
451 m.d.sync += self.o.a.eq(self.dmod.o.a)
452 m.d.sync += self.o.b.eq(self.dmod.o.b)
453
454
455 class FPAddDeNormMod(FPState):
456
457 def __init__(self, width, id_wid):
458 self.width = width
459 self.id_wid = id_wid
460 self.i = self.ispec()
461 self.o = self.ospec()
462
463 def ispec(self):
464 return FPNumBase2Ops(self.width, self.id_wid)
465
466 def ospec(self):
467 return FPNumBase2Ops(self.width, self.id_wid)
468
469 def setup(self, m, in_a, in_b):
470 """ links module to inputs and outputs
471 """
472 m.submodules.denormalise = self
473 m.d.comb += self.i.a.eq(in_a)
474 m.d.comb += self.i.b.eq(in_b)
475
476 def elaborate(self, platform):
477 m = Module()
478 m.submodules.denorm_in_a = self.i.a
479 m.submodules.denorm_in_b = self.i.b
480 m.submodules.denorm_out_a = self.o.a
481 m.submodules.denorm_out_b = self.o.b
482 # hmmm, don't like repeating identical code
483 m.d.comb += self.o.a.eq(self.i.a)
484 with m.If(self.i.a.exp_n127):
485 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
486 with m.Else():
487 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
488
489 m.d.comb += self.o.b.eq(self.i.b)
490 with m.If(self.i.b.exp_n127):
491 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
492 with m.Else():
493 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
494
495 return m
496
497
498 class FPAddDeNorm(FPState, FPID):
499
500 def __init__(self, width, id_wid):
501 FPState.__init__(self, "denormalise")
502 FPID.__init__(self, id_wid)
503 self.mod = FPAddDeNormMod(width)
504 self.out_a = FPNumBase(width)
505 self.out_b = FPNumBase(width)
506
507 def setup(self, m, in_a, in_b, in_mid):
508 """ links module to inputs and outputs
509 """
510 self.mod.setup(m, in_a, in_b)
511 if self.in_mid is not None:
512 m.d.comb += self.in_mid.eq(in_mid)
513
514 def action(self, m):
515 self.idsync(m)
516 # Denormalised Number checks
517 m.next = "align"
518 m.d.sync += self.out_a.eq(self.mod.out_a)
519 m.d.sync += self.out_b.eq(self.mod.out_b)
520
521
522 class FPAddAlignMultiMod(FPState):
523
524 def __init__(self, width):
525 self.in_a = FPNumBase(width)
526 self.in_b = FPNumBase(width)
527 self.out_a = FPNumIn(None, width)
528 self.out_b = FPNumIn(None, width)
529 self.exp_eq = Signal(reset_less=True)
530
531 def elaborate(self, platform):
532 # This one however (single-cycle) will do the shift
533 # in one go.
534
535 m = Module()
536
537 m.submodules.align_in_a = self.in_a
538 m.submodules.align_in_b = self.in_b
539 m.submodules.align_out_a = self.out_a
540 m.submodules.align_out_b = self.out_b
541
542 # NOTE: this does *not* do single-cycle multi-shifting,
543 # it *STAYS* in the align state until exponents match
544
545 # exponent of a greater than b: shift b down
546 m.d.comb += self.exp_eq.eq(0)
547 m.d.comb += self.out_a.eq(self.in_a)
548 m.d.comb += self.out_b.eq(self.in_b)
549 agtb = Signal(reset_less=True)
550 altb = Signal(reset_less=True)
551 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
552 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
553 with m.If(agtb):
554 m.d.comb += self.out_b.shift_down(self.in_b)
555 # exponent of b greater than a: shift a down
556 with m.Elif(altb):
557 m.d.comb += self.out_a.shift_down(self.in_a)
558 # exponents equal: move to next stage.
559 with m.Else():
560 m.d.comb += self.exp_eq.eq(1)
561 return m
562
563
564 class FPAddAlignMulti(FPState, FPID):
565
566 def __init__(self, width, id_wid):
567 FPID.__init__(self, id_wid)
568 FPState.__init__(self, "align")
569 self.mod = FPAddAlignMultiMod(width)
570 self.out_a = FPNumIn(None, width)
571 self.out_b = FPNumIn(None, width)
572 self.exp_eq = Signal(reset_less=True)
573
574 def setup(self, m, in_a, in_b, in_mid):
575 """ links module to inputs and outputs
576 """
577 m.submodules.align = self.mod
578 m.d.comb += self.mod.in_a.eq(in_a)
579 m.d.comb += self.mod.in_b.eq(in_b)
580 #m.d.comb += self.out_a.eq(self.mod.out_a)
581 #m.d.comb += self.out_b.eq(self.mod.out_b)
582 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
583 if self.in_mid is not None:
584 m.d.comb += self.in_mid.eq(in_mid)
585
586 def action(self, m):
587 self.idsync(m)
588 m.d.sync += self.out_a.eq(self.mod.out_a)
589 m.d.sync += self.out_b.eq(self.mod.out_b)
590 with m.If(self.exp_eq):
591 m.next = "add_0"
592
593
594 class FPNumIn2Ops:
595
596 def __init__(self, width, id_wid):
597 self.a = FPNumIn(None, width)
598 self.b = FPNumIn(None, width)
599 self.mid = Signal(id_wid, reset_less=True)
600
601 def eq(self, i):
602 return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
603
604
605 class FPAddAlignSingleMod:
606
607 def __init__(self, width, id_wid):
608 self.width = width
609 self.id_wid = id_wid
610 self.i = self.ispec()
611 self.o = self.ospec()
612
613 def ispec(self):
614 return FPNumBase2Ops(self.width, self.id_wid)
615
616 def ospec(self):
617 return FPNumIn2Ops(self.width, self.id_wid)
618
619 def setup(self, m, in_a, in_b):
620 """ links module to inputs and outputs
621 """
622 m.submodules.align = self
623 m.d.comb += self.i.a.eq(in_a)
624 m.d.comb += self.i.b.eq(in_b)
625
626 def elaborate(self, platform):
627 """ Aligns A against B or B against A, depending on which has the
628 greater exponent. This is done in a *single* cycle using
629 variable-width bit-shift
630
631 the shifter used here is quite expensive in terms of gates.
632 Mux A or B in (and out) into temporaries, as only one of them
633 needs to be aligned against the other
634 """
635 m = Module()
636
637 m.submodules.align_in_a = self.i.a
638 m.submodules.align_in_b = self.i.b
639 m.submodules.align_out_a = self.o.a
640 m.submodules.align_out_b = self.o.b
641
642 # temporary (muxed) input and output to be shifted
643 t_inp = FPNumBase(self.width)
644 t_out = FPNumIn(None, self.width)
645 espec = (len(self.i.a.e), True)
646 msr = MultiShiftRMerge(self.i.a.m_width, espec)
647 m.submodules.align_t_in = t_inp
648 m.submodules.align_t_out = t_out
649 m.submodules.multishift_r = msr
650
651 ediff = Signal(espec, reset_less=True)
652 ediffr = Signal(espec, reset_less=True)
653 tdiff = Signal(espec, reset_less=True)
654 elz = Signal(reset_less=True)
655 egz = Signal(reset_less=True)
656
657 # connect multi-shifter to t_inp/out mantissa (and tdiff)
658 m.d.comb += msr.inp.eq(t_inp.m)
659 m.d.comb += msr.diff.eq(tdiff)
660 m.d.comb += t_out.m.eq(msr.m)
661 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
662 m.d.comb += t_out.s.eq(t_inp.s)
663
664 m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
665 m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
666 m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
667 m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
668
669 # default: A-exp == B-exp, A and B untouched (fall through)
670 m.d.comb += self.o.a.eq(self.i.a)
671 m.d.comb += self.o.b.eq(self.i.b)
672 # only one shifter (muxed)
673 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
674 # exponent of a greater than b: shift b down
675 with m.If(egz):
676 m.d.comb += [t_inp.eq(self.i.b),
677 tdiff.eq(ediff),
678 self.o.b.eq(t_out),
679 self.o.b.s.eq(self.i.b.s), # whoops forgot sign
680 ]
681 # exponent of b greater than a: shift a down
682 with m.Elif(elz):
683 m.d.comb += [t_inp.eq(self.i.a),
684 tdiff.eq(ediffr),
685 self.o.a.eq(t_out),
686 self.o.a.s.eq(self.i.a.s), # whoops forgot sign
687 ]
688 return m
689
690
691 class FPAddAlignSingle(FPState, FPID):
692
693 def __init__(self, width, id_wid):
694 FPState.__init__(self, "align")
695 FPID.__init__(self, id_wid)
696 self.mod = FPAddAlignSingleMod(width, id_wid)
697 self.out_a = FPNumIn(None, width)
698 self.out_b = FPNumIn(None, width)
699
700 def setup(self, m, in_a, in_b, in_mid):
701 """ links module to inputs and outputs
702 """
703 self.mod.setup(m, in_a, in_b)
704 if self.in_mid is not None:
705 m.d.comb += self.in_mid.eq(in_mid)
706
707 def action(self, m):
708 self.idsync(m)
709 # NOTE: could be done as comb
710 m.d.sync += self.out_a.eq(self.mod.out_a)
711 m.d.sync += self.out_b.eq(self.mod.out_b)
712 m.next = "add_0"
713
714
715 class FPAddAlignSingleAdd(FPState, FPID):
716
717 def __init__(self, width, id_wid):
718 FPState.__init__(self, "align")
719 FPID.__init__(self, id_wid)
720 self.mod = FPAddAlignSingleMod(width, id_wid)
721 self.o = self.mod.ospec()
722
723 self.a0mod = FPAddStage0Mod(width, id_wid)
724 self.a0o = self.a0mod.ospec()
725
726 self.a1mod = FPAddStage1Mod(width, id_wid)
727 self.a1o = self.a1mod.ospec()
728
729 def setup(self, m, in_a, in_b, in_mid):
730 """ links module to inputs and outputs
731 """
732 self.mod.setup(m, in_a, in_b)
733 m.d.comb += self.o.eq(self.mod.o)
734
735 self.a0mod.setup(m, self.o.a, self.o.b)
736 m.d.comb += self.a0o.eq(self.a0mod.o)
737
738 self.a1mod.setup(m, self.a0o.tot, self.a0o.z)
739
740 if self.in_mid is not None:
741 m.d.comb += self.in_mid.eq(in_mid)
742
743 def action(self, m):
744 self.idsync(m)
745 m.d.sync += self.a1o.eq(self.a1mod.o)
746 m.next = "normalise_1"
747
748
749 class FPAddStage0Data:
750
751 def __init__(self, width, id_wid):
752 self.z = FPNumBase(width, False)
753 self.tot = Signal(self.z.m_width + 4, reset_less=True)
754 self.mid = Signal(id_wid, reset_less=True)
755
756 def eq(self, i):
757 return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
758
759
760 class FPAddStage0Mod:
761
762 def __init__(self, width, id_wid):
763 self.width = width
764 self.id_wid = id_wid
765 self.i = self.ispec()
766 self.o = self.ospec()
767
768 def ispec(self):
769 return FPNumBase2Ops(self.width, self.id_wid)
770
771 def ospec(self):
772 return FPAddStage0Data(self.width, self.id_wid)
773
774 def setup(self, m, in_a, in_b):
775 """ links module to inputs and outputs
776 """
777 m.submodules.add0 = self
778 m.d.comb += self.i.a.eq(in_a)
779 m.d.comb += self.i.b.eq(in_b)
780
781 def elaborate(self, platform):
782 m = Module()
783 m.submodules.add0_in_a = self.i.a
784 m.submodules.add0_in_b = self.i.b
785 m.submodules.add0_out_z = self.o.z
786
787 m.d.comb += self.o.z.e.eq(self.i.a.e)
788
789 # store intermediate tests (and zero-extended mantissas)
790 seq = Signal(reset_less=True)
791 mge = Signal(reset_less=True)
792 am0 = Signal(len(self.i.a.m)+1, reset_less=True)
793 bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
794 m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
795 mge.eq(self.i.a.m >= self.i.b.m),
796 am0.eq(Cat(self.i.a.m, 0)),
797 bm0.eq(Cat(self.i.b.m, 0))
798 ]
799 # same-sign (both negative or both positive) add mantissas
800 with m.If(seq):
801 m.d.comb += [
802 self.o.tot.eq(am0 + bm0),
803 self.o.z.s.eq(self.i.a.s)
804 ]
805 # a mantissa greater than b, use a
806 with m.Elif(mge):
807 m.d.comb += [
808 self.o.tot.eq(am0 - bm0),
809 self.o.z.s.eq(self.i.a.s)
810 ]
811 # b mantissa greater than a, use b
812 with m.Else():
813 m.d.comb += [
814 self.o.tot.eq(bm0 - am0),
815 self.o.z.s.eq(self.i.b.s)
816 ]
817 return m
818
819
820 class FPAddStage0(FPState, FPID):
821 """ First stage of add. covers same-sign (add) and subtract
822 special-casing when mantissas are greater or equal, to
823 give greatest accuracy.
824 """
825
826 def __init__(self, width, id_wid):
827 FPState.__init__(self, "add_0")
828 FPID.__init__(self, id_wid)
829 self.mod = FPAddStage0Mod(width)
830 self.o = self.mod.ospec()
831
832 def setup(self, m, in_a, in_b, in_mid):
833 """ links module to inputs and outputs
834 """
835 self.mod.setup(m, in_a, in_b)
836 if self.in_mid is not None:
837 m.d.comb += self.in_mid.eq(in_mid)
838
839 def action(self, m):
840 self.idsync(m)
841 # NOTE: these could be done as combinatorial (merge add0+add1)
842 m.d.sync += self.o.eq(self.mod.o)
843 m.next = "add_1"
844
845
846 class FPAddStage1Data:
847
848 def __init__(self, width, id_wid):
849 self.z = FPNumBase(width, False)
850 self.of = Overflow()
851 self.mid = Signal(id_wid, reset_less=True)
852
853 def eq(self, i):
854 return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
855
856
857
858 class FPAddStage1Mod(FPState):
859 """ Second stage of add: preparation for normalisation.
860 detects when tot sum is too big (tot[27] is kinda a carry bit)
861 """
862
863 def __init__(self, width, id_wid):
864 self.width = width
865 self.id_wid = id_wid
866 self.i = self.ispec()
867 self.o = self.ospec()
868
869 def ispec(self):
870 return FPAddStage0Data(self.width, self.id_wid)
871
872 def ospec(self):
873 return FPAddStage1Data(self.width, self.id_wid)
874
875 def setup(self, m, in_tot, in_z):
876 """ links module to inputs and outputs
877 """
878 m.submodules.add1 = self
879 m.submodules.add1_out_overflow = self.o.of
880
881 m.d.comb += self.i.z.eq(in_z)
882 m.d.comb += self.i.tot.eq(in_tot)
883
884 def elaborate(self, platform):
885 m = Module()
886 #m.submodules.norm1_in_overflow = self.in_of
887 #m.submodules.norm1_out_overflow = self.out_of
888 #m.submodules.norm1_in_z = self.in_z
889 #m.submodules.norm1_out_z = self.out_z
890 m.d.comb += self.o.z.eq(self.i.z)
891 # tot[-1] (MSB) gets set when the sum overflows. shift result down
892 with m.If(self.i.tot[-1]):
893 m.d.comb += [
894 self.o.z.m.eq(self.i.tot[4:]),
895 self.o.of.m0.eq(self.i.tot[4]),
896 self.o.of.guard.eq(self.i.tot[3]),
897 self.o.of.round_bit.eq(self.i.tot[2]),
898 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
899 self.o.z.e.eq(self.i.z.e + 1)
900 ]
901 # tot[-1] (MSB) zero case
902 with m.Else():
903 m.d.comb += [
904 self.o.z.m.eq(self.i.tot[3:]),
905 self.o.of.m0.eq(self.i.tot[3]),
906 self.o.of.guard.eq(self.i.tot[2]),
907 self.o.of.round_bit.eq(self.i.tot[1]),
908 self.o.of.sticky.eq(self.i.tot[0])
909 ]
910 return m
911
912
913 class FPAddStage1(FPState, FPID):
914
915 def __init__(self, width, id_wid):
916 FPState.__init__(self, "add_1")
917 FPID.__init__(self, id_wid)
918 self.mod = FPAddStage1Mod(width)
919 self.out_z = FPNumBase(width, False)
920 self.out_of = Overflow()
921 self.norm_stb = Signal()
922
923 def setup(self, m, in_tot, in_z, in_mid):
924 """ links module to inputs and outputs
925 """
926 self.mod.setup(m, in_tot, in_z)
927
928 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
929
930 if self.in_mid is not None:
931 m.d.comb += self.in_mid.eq(in_mid)
932
933 def action(self, m):
934 self.idsync(m)
935 m.d.sync += self.out_of.eq(self.mod.out_of)
936 m.d.sync += self.out_z.eq(self.mod.out_z)
937 m.d.sync += self.norm_stb.eq(1)
938 m.next = "normalise_1"
939
940
941 class FPNormaliseModSingle:
942
943 def __init__(self, width):
944 self.width = width
945 self.in_z = self.ispec()
946 self.out_z = self.ospec()
947
948 def ispec(self):
949 return FPNumBase(self.width, False)
950
951 def ospec(self):
952 return FPNumBase(self.width, False)
953
954 def setup(self, m, in_z, out_z):
955 """ links module to inputs and outputs
956 """
957 m.submodules.normalise = self
958 m.d.comb += self.in_z.eq(in_z)
959 m.d.comb += out_z.eq(self.out_z)
960
961 def elaborate(self, platform):
962 m = Module()
963
964 mwid = self.out_z.m_width+2
965 pe = PriorityEncoder(mwid)
966 m.submodules.norm_pe = pe
967
968 m.submodules.norm1_out_z = self.out_z
969 m.submodules.norm1_in_z = self.in_z
970
971 in_z = FPNumBase(self.width, False)
972 in_of = Overflow()
973 m.submodules.norm1_insel_z = in_z
974 m.submodules.norm1_insel_overflow = in_of
975
976 espec = (len(in_z.e), True)
977 ediff_n126 = Signal(espec, reset_less=True)
978 msr = MultiShiftRMerge(mwid, espec)
979 m.submodules.multishift_r = msr
980
981 m.d.comb += in_z.eq(self.in_z)
982 m.d.comb += in_of.eq(self.in_of)
983 # initialise out from in (overridden below)
984 m.d.comb += self.out_z.eq(in_z)
985 m.d.comb += self.out_of.eq(in_of)
986 # normalisation decrease condition
987 decrease = Signal(reset_less=True)
988 m.d.comb += decrease.eq(in_z.m_msbzero)
989 # decrease exponent
990 with m.If(decrease):
991 # *sigh* not entirely obvious: count leading zeros (clz)
992 # with a PriorityEncoder: to find from the MSB
993 # we reverse the order of the bits.
994 temp_m = Signal(mwid, reset_less=True)
995 temp_s = Signal(mwid+1, reset_less=True)
996 clz = Signal((len(in_z.e), True), reset_less=True)
997 m.d.comb += [
998 # cat round and guard bits back into the mantissa
999 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1000 pe.i.eq(temp_m[::-1]), # inverted
1001 clz.eq(pe.o), # count zeros from MSB down
1002 temp_s.eq(temp_m << clz), # shift mantissa UP
1003 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1004 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1005 ]
1006
1007 return m
1008
1009 class FPNorm1Data:
1010
1011 def __init__(self, width, id_wid):
1012 self.roundz = Signal(reset_less=True)
1013 self.z = FPNumBase(width, False)
1014 self.mid = Signal(id_wid, reset_less=True)
1015
1016 def eq(self, i):
1017 return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1018
1019
1020 class FPNorm1ModSingle:
1021
1022 def __init__(self, width, id_wid):
1023 self.width = width
1024 self.id_wid = id_wid
1025 self.i = self.ispec()
1026 self.o = self.ospec()
1027
1028 def ispec(self):
1029 return FPAddStage1Data(self.width, self.id_wid)
1030
1031 def ospec(self):
1032 return FPNorm1Data(self.width, self.id_wid)
1033
1034 def setup(self, m, in_z, in_of, out_z):
1035 """ links module to inputs and outputs
1036 """
1037 m.submodules.normalise_1 = self
1038
1039 m.d.comb += self.i.z.eq(in_z)
1040 m.d.comb += self.i.of.eq(in_of)
1041
1042 m.d.comb += out_z.eq(self.o.z)
1043
1044 def elaborate(self, platform):
1045 m = Module()
1046
1047 mwid = self.o.z.m_width+2
1048 pe = PriorityEncoder(mwid)
1049 m.submodules.norm_pe = pe
1050
1051 of = Overflow()
1052 m.d.comb += self.o.roundz.eq(of.roundz)
1053
1054 m.submodules.norm1_out_z = self.o.z
1055 m.submodules.norm1_out_overflow = of
1056 m.submodules.norm1_in_z = self.i.z
1057 m.submodules.norm1_in_overflow = self.i.of
1058
1059 i = self.ispec()
1060 m.submodules.norm1_insel_z = i.z
1061 m.submodules.norm1_insel_overflow = i.of
1062
1063 espec = (len(i.z.e), True)
1064 ediff_n126 = Signal(espec, reset_less=True)
1065 msr = MultiShiftRMerge(mwid, espec)
1066 m.submodules.multishift_r = msr
1067
1068 m.d.comb += i.eq(self.i)
1069 # initialise out from in (overridden below)
1070 m.d.comb += self.o.z.eq(i.z)
1071 m.d.comb += of.eq(i.of)
1072 # normalisation increase/decrease conditions
1073 decrease = Signal(reset_less=True)
1074 increase = Signal(reset_less=True)
1075 m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1076 m.d.comb += increase.eq(i.z.exp_lt_n126)
1077 # decrease exponent
1078 with m.If(decrease):
1079 # *sigh* not entirely obvious: count leading zeros (clz)
1080 # with a PriorityEncoder: to find from the MSB
1081 # we reverse the order of the bits.
1082 temp_m = Signal(mwid, reset_less=True)
1083 temp_s = Signal(mwid+1, reset_less=True)
1084 clz = Signal((len(i.z.e), True), reset_less=True)
1085 # make sure that the amount to decrease by does NOT
1086 # go below the minimum non-INF/NaN exponent
1087 limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1088 i.z.exp_sub_n126)
1089 m.d.comb += [
1090 # cat round and guard bits back into the mantissa
1091 temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1092 pe.i.eq(temp_m[::-1]), # inverted
1093 clz.eq(limclz), # count zeros from MSB down
1094 temp_s.eq(temp_m << clz), # shift mantissa UP
1095 self.o.z.e.eq(i.z.e - clz), # DECREASE exponent
1096 self.o.z.m.eq(temp_s[2:]), # exclude bits 0&1
1097 of.m0.eq(temp_s[2]), # copy of mantissa[0]
1098 # overflow in bits 0..1: got shifted too (leave sticky)
1099 of.guard.eq(temp_s[1]), # guard
1100 of.round_bit.eq(temp_s[0]), # round
1101 ]
1102 # increase exponent
1103 with m.Elif(increase):
1104 temp_m = Signal(mwid+1, reset_less=True)
1105 m.d.comb += [
1106 temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1107 i.z.m)),
1108 ediff_n126.eq(i.z.N126 - i.z.e),
1109 # connect multi-shifter to inp/out mantissa (and ediff)
1110 msr.inp.eq(temp_m),
1111 msr.diff.eq(ediff_n126),
1112 self.o.z.m.eq(msr.m[3:]),
1113 of.m0.eq(temp_s[3]), # copy of mantissa[0]
1114 # overflow in bits 0..1: got shifted too (leave sticky)
1115 of.guard.eq(temp_s[2]), # guard
1116 of.round_bit.eq(temp_s[1]), # round
1117 of.sticky.eq(temp_s[0]), # sticky
1118 self.o.z.e.eq(i.z.e + ediff_n126),
1119 ]
1120
1121 return m
1122
1123
1124 class FPNorm1ModMulti:
1125
1126 def __init__(self, width, single_cycle=True):
1127 self.width = width
1128 self.in_select = Signal(reset_less=True)
1129 self.in_z = FPNumBase(width, False)
1130 self.in_of = Overflow()
1131 self.temp_z = FPNumBase(width, False)
1132 self.temp_of = Overflow()
1133 self.out_z = FPNumBase(width, False)
1134 self.out_of = Overflow()
1135
1136 def elaborate(self, platform):
1137 m = Module()
1138
1139 m.submodules.norm1_out_z = self.out_z
1140 m.submodules.norm1_out_overflow = self.out_of
1141 m.submodules.norm1_temp_z = self.temp_z
1142 m.submodules.norm1_temp_of = self.temp_of
1143 m.submodules.norm1_in_z = self.in_z
1144 m.submodules.norm1_in_overflow = self.in_of
1145
1146 in_z = FPNumBase(self.width, False)
1147 in_of = Overflow()
1148 m.submodules.norm1_insel_z = in_z
1149 m.submodules.norm1_insel_overflow = in_of
1150
1151 # select which of temp or in z/of to use
1152 with m.If(self.in_select):
1153 m.d.comb += in_z.eq(self.in_z)
1154 m.d.comb += in_of.eq(self.in_of)
1155 with m.Else():
1156 m.d.comb += in_z.eq(self.temp_z)
1157 m.d.comb += in_of.eq(self.temp_of)
1158 # initialise out from in (overridden below)
1159 m.d.comb += self.out_z.eq(in_z)
1160 m.d.comb += self.out_of.eq(in_of)
1161 # normalisation increase/decrease conditions
1162 decrease = Signal(reset_less=True)
1163 increase = Signal(reset_less=True)
1164 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1165 m.d.comb += increase.eq(in_z.exp_lt_n126)
1166 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1167 # decrease exponent
1168 with m.If(decrease):
1169 m.d.comb += [
1170 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1171 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1172 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1173 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1174 self.out_of.round_bit.eq(0), # reset round bit
1175 self.out_of.m0.eq(in_of.guard),
1176 ]
1177 # increase exponent
1178 with m.Elif(increase):
1179 m.d.comb += [
1180 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1181 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1182 self.out_of.guard.eq(in_z.m[0]),
1183 self.out_of.m0.eq(in_z.m[1]),
1184 self.out_of.round_bit.eq(in_of.guard),
1185 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1186 ]
1187
1188 return m
1189
1190
1191 class FPNorm1Single(FPState, FPID):
1192
1193 def __init__(self, width, id_wid, single_cycle=True):
1194 FPID.__init__(self, id_wid)
1195 FPState.__init__(self, "normalise_1")
1196 self.mod = FPNorm1ModSingle(width)
1197 self.out_z = FPNumBase(width, False)
1198 self.out_roundz = Signal(reset_less=True)
1199
1200 def setup(self, m, in_z, in_of, in_mid):
1201 """ links module to inputs and outputs
1202 """
1203 self.mod.setup(m, in_z, in_of, self.out_z)
1204
1205 if self.in_mid is not None:
1206 m.d.comb += self.in_mid.eq(in_mid)
1207
1208 def action(self, m):
1209 self.idsync(m)
1210 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1211 m.next = "round"
1212
1213
1214 class FPNorm1Multi(FPState, FPID):
1215
1216 def __init__(self, width, id_wid):
1217 FPID.__init__(self, id_wid)
1218 FPState.__init__(self, "normalise_1")
1219 self.mod = FPNorm1ModMulti(width)
1220 self.stb = Signal(reset_less=True)
1221 self.ack = Signal(reset=0, reset_less=True)
1222 self.out_norm = Signal(reset_less=True)
1223 self.in_accept = Signal(reset_less=True)
1224 self.temp_z = FPNumBase(width)
1225 self.temp_of = Overflow()
1226 self.out_z = FPNumBase(width)
1227 self.out_roundz = Signal(reset_less=True)
1228
1229 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1230 """ links module to inputs and outputs
1231 """
1232 self.mod.setup(m, in_z, in_of, norm_stb,
1233 self.in_accept, self.temp_z, self.temp_of,
1234 self.out_z, self.out_norm)
1235
1236 m.d.comb += self.stb.eq(norm_stb)
1237 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1238
1239 if self.in_mid is not None:
1240 m.d.comb += self.in_mid.eq(in_mid)
1241
1242 def action(self, m):
1243 self.idsync(m)
1244 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1245 m.d.sync += self.temp_of.eq(self.mod.out_of)
1246 m.d.sync += self.temp_z.eq(self.out_z)
1247 with m.If(self.out_norm):
1248 with m.If(self.in_accept):
1249 m.d.sync += [
1250 self.ack.eq(1),
1251 ]
1252 with m.Else():
1253 m.d.sync += self.ack.eq(0)
1254 with m.Else():
1255 # normalisation not required (or done).
1256 m.next = "round"
1257 m.d.sync += self.ack.eq(1)
1258 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1259
1260
1261 class FPNormToPack(FPState, FPID):
1262
1263 def __init__(self, width, id_wid):
1264 FPID.__init__(self, id_wid)
1265 FPState.__init__(self, "normalise_1")
1266 self.width = width
1267
1268 def setup(self, m, in_z, in_of, in_mid):
1269 """ links module to inputs and outputs
1270 """
1271
1272 # Normalisation (chained to input in_z+in_of)
1273 nmod = FPNorm1ModSingle(self.width, self.id_wid)
1274 n_out = nmod.ospec()
1275 nmod.setup(m, in_z, in_of, n_out.z)
1276 m.d.comb += n_out.roundz.eq(nmod.o.roundz)
1277
1278 # Rounding (chained to normalisation)
1279 rmod = FPRoundMod(self.width, self.id_wid)
1280 r_out_z = rmod.ospec()
1281 rmod.setup(m, n_out.z, n_out.roundz)
1282 m.d.comb += r_out_z.eq(rmod.out_z)
1283
1284 # Corrections (chained to rounding)
1285 cmod = FPCorrectionsMod(self.width, self.id_wid)
1286 c_out_z = cmod.ospec()
1287 cmod.setup(m, r_out_z)
1288 m.d.comb += c_out_z.eq(cmod.out_z)
1289
1290 # Pack (chained to corrections)
1291 self.pmod = FPPackMod(self.width, self.id_wid)
1292 self.out_z = self.pmod.ospec()
1293 self.pmod.setup(m, c_out_z)
1294
1295 # Multiplex ID
1296 if self.in_mid is not None:
1297 m.d.comb += self.in_mid.eq(in_mid)
1298
1299 def action(self, m):
1300 self.idsync(m) # copies incoming ID to outgoing
1301 m.d.sync += self.out_z.z.v.eq(self.pmod.o.z.v) # outputs packed result
1302 m.next = "pack_put_z"
1303
1304
1305 class FPRoundData:
1306
1307 def __init__(self, width, id_wid):
1308 self.z = FPNumBase(width, False)
1309 self.mid = Signal(id_wid, reset_less=True)
1310
1311 def eq(self, i):
1312 return [self.z.eq(i.z), self.mid.eq(i.mid)]
1313
1314
1315 class FPRoundMod:
1316
1317 def __init__(self, width, id_wid):
1318 self.width = width
1319 self.id_wid = id_wid
1320 self.i = self.ispec()
1321 self.out_z = self.ospec()
1322
1323 def ispec(self):
1324 return FPNorm1Data(self.width, self.id_wid)
1325
1326 def ospec(self):
1327 return FPRoundData(self.width, self.id_wid)
1328
1329 def setup(self, m, in_z, roundz):
1330 m.submodules.roundz = self
1331
1332 m.d.comb += self.i.z.eq(in_z)
1333 m.d.comb += self.i.roundz.eq(roundz)
1334
1335 def elaborate(self, platform):
1336 m = Module()
1337 m.d.comb += self.out_z.eq(self.i)
1338 with m.If(self.i.roundz):
1339 m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
1340 with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1341 m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1342 return m
1343
1344
1345 class FPRound(FPState, FPID):
1346
1347 def __init__(self, width, id_wid):
1348 FPState.__init__(self, "round")
1349 FPID.__init__(self, id_wid)
1350 self.mod = FPRoundMod(width)
1351 self.out_z = self.mod.ospec()
1352
1353 def setup(self, m, in_z, roundz, in_mid):
1354 """ links module to inputs and outputs
1355 """
1356 self.mod.setup(m, in_z, roundz)
1357
1358 if self.in_mid is not None:
1359 m.d.comb += self.in_mid.eq(in_mid)
1360
1361 def action(self, m):
1362 self.idsync(m)
1363 m.d.sync += self.out_z.eq(self.mod.out_z)
1364 m.next = "corrections"
1365
1366
1367 class FPCorrectionsMod:
1368
1369 def __init__(self, width, id_wid):
1370 self.width = width
1371 self.id_wid = id_wid
1372 self.in_z = self.ispec()
1373 self.out_z = self.ospec()
1374
1375 def ispec(self):
1376 return FPRoundData(self.width, self.id_wid)
1377
1378 def ospec(self):
1379 return FPRoundData(self.width, self.id_wid)
1380
1381 def setup(self, m, in_z):
1382 """ links module to inputs and outputs
1383 """
1384 m.submodules.corrections = self
1385 m.d.comb += self.in_z.eq(in_z)
1386
1387 def elaborate(self, platform):
1388 m = Module()
1389 m.submodules.corr_in_z = self.in_z.z
1390 m.submodules.corr_out_z = self.out_z.z
1391 m.d.comb += self.out_z.eq(self.in_z)
1392 with m.If(self.in_z.z.is_denormalised):
1393 m.d.comb += self.out_z.z.e.eq(self.in_z.z.N127)
1394 return m
1395
1396
1397 class FPCorrections(FPState, FPID):
1398
1399 def __init__(self, width, id_wid):
1400 FPState.__init__(self, "corrections")
1401 FPID.__init__(self, id_wid)
1402 self.mod = FPCorrectionsMod(width)
1403 self.out_z = self.mod.ospec()
1404
1405 def setup(self, m, in_z, in_mid):
1406 """ links module to inputs and outputs
1407 """
1408 self.mod.setup(m, in_z)
1409 if self.in_mid is not None:
1410 m.d.comb += self.in_mid.eq(in_mid)
1411
1412 def action(self, m):
1413 self.idsync(m)
1414 m.d.sync += self.out_z.eq(self.mod.out_z)
1415 m.next = "pack"
1416
1417
1418 class FPPackData:
1419
1420 def __init__(self, width, id_wid):
1421 self.z = FPNumOut(width, False)
1422 self.mid = Signal(id_wid, reset_less=True)
1423
1424 def eq(self, i):
1425 return [self.z.eq(i.z), self.mid.eq(i.mid)]
1426
1427
1428 class FPPackMod:
1429
1430 def __init__(self, width, id_wid):
1431 self.width = width
1432 self.id_wid = id_wid
1433 self.i = self.ispec()
1434 self.o = self.ospec()
1435
1436 def ispec(self):
1437 return FPRoundData(self.width, self.id_wid)
1438
1439 def ospec(self):
1440 return FPPackData(self.width, self.id_wid)
1441
1442 def setup(self, m, in_z):
1443 """ links module to inputs and outputs
1444 """
1445 m.submodules.pack = self
1446 m.d.comb += self.i.eq(in_z)
1447
1448 def elaborate(self, platform):
1449 m = Module()
1450 m.submodules.pack_in_z = self.i.z
1451 with m.If(self.i.z.is_overflowed):
1452 m.d.comb += self.o.z.inf(self.i.z.s)
1453 with m.Else():
1454 m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1455 return m
1456
1457
1458 class FPPackData:
1459 def __init__(self, width, id_wid):
1460 self.z = FPNumOut(width, False)
1461 self.mid = Signal(id_wid, reset_less=True)
1462
1463 def eq(self, i):
1464 return [self.z.eq(i.z), self.mid.eq(i.mid)]
1465
1466
1467 class FPPack(FPState, FPID):
1468
1469 def __init__(self, width, id_wid):
1470 FPState.__init__(self, "pack")
1471 FPID.__init__(self, id_wid)
1472 self.mod = FPPackMod(width)
1473 self.out_z = self.ospec()
1474
1475 def ispec(self):
1476 return self.mod.ispec()
1477
1478 def ospec(self):
1479 return self.mod.ospec()
1480
1481 def setup(self, m, in_z, in_mid):
1482 """ links module to inputs and outputs
1483 """
1484 self.mod.setup(m, in_z)
1485 if self.in_mid is not None:
1486 m.d.comb += self.in_mid.eq(in_mid)
1487
1488 def action(self, m):
1489 self.idsync(m)
1490 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1491 m.next = "pack_put_z"
1492
1493
1494 class FPPutZ(FPState):
1495
1496 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1497 FPState.__init__(self, state)
1498 if to_state is None:
1499 to_state = "get_ops"
1500 self.to_state = to_state
1501 self.in_z = in_z
1502 self.out_z = out_z
1503 self.in_mid = in_mid
1504 self.out_mid = out_mid
1505
1506 def action(self, m):
1507 if self.in_mid is not None:
1508 m.d.sync += self.out_mid.eq(self.in_mid)
1509 m.d.sync += [
1510 self.out_z.v.eq(self.in_z.v)
1511 ]
1512 with m.If(self.out_z.stb & self.out_z.ack):
1513 m.d.sync += self.out_z.stb.eq(0)
1514 m.next = self.to_state
1515 with m.Else():
1516 m.d.sync += self.out_z.stb.eq(1)
1517
1518
1519 class FPPutZIdx(FPState):
1520
1521 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1522 FPState.__init__(self, state)
1523 if to_state is None:
1524 to_state = "get_ops"
1525 self.to_state = to_state
1526 self.in_z = in_z
1527 self.out_zs = out_zs
1528 self.in_mid = in_mid
1529
1530 def action(self, m):
1531 outz_stb = Signal(reset_less=True)
1532 outz_ack = Signal(reset_less=True)
1533 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1534 outz_ack.eq(self.out_zs[self.in_mid].ack),
1535 ]
1536 m.d.sync += [
1537 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1538 ]
1539 with m.If(outz_stb & outz_ack):
1540 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1541 m.next = self.to_state
1542 with m.Else():
1543 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1544
1545
1546 class FPADDBaseMod(FPID):
1547
1548 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1549 """ IEEE754 FP Add
1550
1551 * width: bit-width of IEEE754. supported: 16, 32, 64
1552 * id_wid: an identifier that is sync-connected to the input
1553 * single_cycle: True indicates each stage to complete in 1 clock
1554 * compact: True indicates a reduced number of stages
1555 """
1556 FPID.__init__(self, id_wid)
1557 self.width = width
1558 self.single_cycle = single_cycle
1559 self.compact = compact
1560
1561 self.in_t = Trigger()
1562 self.in_a = Signal(width)
1563 self.in_b = Signal(width)
1564 self.out_z = FPOp(width)
1565
1566 self.states = []
1567
1568 def add_state(self, state):
1569 self.states.append(state)
1570 return state
1571
1572 def get_fragment(self, platform=None):
1573 """ creates the HDL code-fragment for FPAdd
1574 """
1575 m = Module()
1576 m.submodules.out_z = self.out_z
1577 m.submodules.in_t = self.in_t
1578 if self.compact:
1579 self.get_compact_fragment(m, platform)
1580 else:
1581 self.get_longer_fragment(m, platform)
1582
1583 with m.FSM() as fsm:
1584
1585 for state in self.states:
1586 with m.State(state.state_from):
1587 state.action(m)
1588
1589 return m
1590
1591 def get_longer_fragment(self, m, platform=None):
1592
1593 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1594 self.in_a, self.in_b, self.width))
1595 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1596 a = get.out_op1
1597 b = get.out_op2
1598
1599 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1600 sc.setup(m, a, b, self.in_mid)
1601
1602 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1603 dn.setup(m, a, b, sc.in_mid)
1604
1605 if self.single_cycle:
1606 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1607 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1608 else:
1609 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1610 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1611
1612 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1613 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1614
1615 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1616 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1617
1618 if self.single_cycle:
1619 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1620 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1621 else:
1622 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1623 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1624
1625 rn = self.add_state(FPRound(self.width, self.id_wid))
1626 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1627
1628 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1629 cor.setup(m, rn.out_z, rn.in_mid)
1630
1631 pa = self.add_state(FPPack(self.width, self.id_wid))
1632 pa.setup(m, cor.out_z, rn.in_mid)
1633
1634 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1635 pa.in_mid, self.out_mid))
1636
1637 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1638 pa.in_mid, self.out_mid))
1639
1640 def get_compact_fragment(self, m, platform=None):
1641
1642 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1643 self.in_a, self.in_b,
1644 self.width, self.id_wid))
1645 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1646 a = get.o.a
1647 b = get.o.b
1648
1649 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1650 sc.setup(m, a, b, self.in_mid)
1651
1652 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1653 alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
1654
1655 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1656 n1.setup(m, alm.a1o.z, alm.a1o.of, alm.in_mid)
1657
1658 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.out_z,
1659 n1.in_mid, self.out_mid))
1660
1661 pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.out_z,
1662 sc.in_mid, self.out_mid))
1663
1664
1665 class FPADDBase(FPState, FPID):
1666
1667 def __init__(self, width, id_wid=None, single_cycle=False):
1668 """ IEEE754 FP Add
1669
1670 * width: bit-width of IEEE754. supported: 16, 32, 64
1671 * id_wid: an identifier that is sync-connected to the input
1672 * single_cycle: True indicates each stage to complete in 1 clock
1673 """
1674 FPID.__init__(self, id_wid)
1675 FPState.__init__(self, "fpadd")
1676 self.width = width
1677 self.single_cycle = single_cycle
1678 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1679
1680 self.in_t = Trigger()
1681 self.in_a = Signal(width)
1682 self.in_b = Signal(width)
1683 #self.out_z = FPOp(width)
1684
1685 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1686 self.in_accept = Signal(reset_less=True)
1687 self.add_stb = Signal(reset_less=True)
1688 self.add_ack = Signal(reset=0, reset_less=True)
1689
1690 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1691 self.out_z = out_z
1692 self.out_mid = out_mid
1693 m.d.comb += [self.in_a.eq(a),
1694 self.in_b.eq(b),
1695 self.mod.in_a.eq(self.in_a),
1696 self.mod.in_b.eq(self.in_b),
1697 self.in_mid.eq(in_mid),
1698 self.mod.in_mid.eq(self.in_mid),
1699 self.z_done.eq(self.mod.out_z.trigger),
1700 #self.add_stb.eq(add_stb),
1701 self.mod.in_t.stb.eq(self.in_t.stb),
1702 self.in_t.ack.eq(self.mod.in_t.ack),
1703 self.out_mid.eq(self.mod.out_mid),
1704 self.out_z.v.eq(self.mod.out_z.v),
1705 self.out_z.stb.eq(self.mod.out_z.stb),
1706 self.mod.out_z.ack.eq(self.out_z.ack),
1707 ]
1708
1709 m.d.sync += self.add_stb.eq(add_stb)
1710 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1711 m.d.sync += self.out_z.ack.eq(0) # likewise
1712 #m.d.sync += self.in_t.stb.eq(0)
1713
1714 m.submodules.fpadd = self.mod
1715
1716 def action(self, m):
1717
1718 # in_accept is set on incoming strobe HIGH and ack LOW.
1719 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1720
1721 #with m.If(self.in_t.ack):
1722 # m.d.sync += self.in_t.stb.eq(0)
1723 with m.If(~self.z_done):
1724 # not done: test for accepting an incoming operand pair
1725 with m.If(self.in_accept):
1726 m.d.sync += [
1727 self.add_ack.eq(1), # acknowledge receipt...
1728 self.in_t.stb.eq(1), # initiate add
1729 ]
1730 with m.Else():
1731 m.d.sync += [self.add_ack.eq(0),
1732 self.in_t.stb.eq(0),
1733 self.out_z.ack.eq(1),
1734 ]
1735 with m.Else():
1736 # done: acknowledge, and write out id and value
1737 m.d.sync += [self.add_ack.eq(1),
1738 self.in_t.stb.eq(0)
1739 ]
1740 m.next = "put_z"
1741
1742 return
1743
1744 if self.in_mid is not None:
1745 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1746
1747 m.d.sync += [
1748 self.out_z.v.eq(self.mod.out_z.v)
1749 ]
1750 # move to output state on detecting z ack
1751 with m.If(self.out_z.trigger):
1752 m.d.sync += self.out_z.stb.eq(0)
1753 m.next = "put_z"
1754 with m.Else():
1755 m.d.sync += self.out_z.stb.eq(1)
1756
1757 class ResArray:
1758 def __init__(self, width, id_wid):
1759 self.width = width
1760 self.id_wid = id_wid
1761 res = []
1762 for i in range(rs_sz):
1763 out_z = FPOp(width)
1764 out_z.name = "out_z_%d" % i
1765 res.append(out_z)
1766 self.res = Array(res)
1767 self.in_z = FPOp(width)
1768 self.in_mid = Signal(self.id_wid, reset_less=True)
1769
1770 def setup(self, m, in_z, in_mid):
1771 m.d.comb += [self.in_z.eq(in_z),
1772 self.in_mid.eq(in_mid)]
1773
1774 def get_fragment(self, platform=None):
1775 """ creates the HDL code-fragment for FPAdd
1776 """
1777 m = Module()
1778 m.submodules.res_in_z = self.in_z
1779 m.submodules += self.res
1780
1781 return m
1782
1783 def ports(self):
1784 res = []
1785 for z in self.res:
1786 res += z.ports()
1787 return res
1788
1789
1790 class FPADD(FPID):
1791 """ FPADD: stages as follows:
1792
1793 FPGetOp (a)
1794 |
1795 FPGetOp (b)
1796 |
1797 FPAddBase---> FPAddBaseMod
1798 | |
1799 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1800
1801 FPAddBase is tricky: it is both a stage and *has* stages.
1802 Connection to FPAddBaseMod therefore requires an in stb/ack
1803 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1804 needs to be the thing that raises the incoming stb.
1805 """
1806
1807 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1808 """ IEEE754 FP Add
1809
1810 * width: bit-width of IEEE754. supported: 16, 32, 64
1811 * id_wid: an identifier that is sync-connected to the input
1812 * single_cycle: True indicates each stage to complete in 1 clock
1813 """
1814 self.width = width
1815 self.id_wid = id_wid
1816 self.single_cycle = single_cycle
1817
1818 #self.out_z = FPOp(width)
1819 self.ids = FPID(id_wid)
1820
1821 rs = []
1822 for i in range(rs_sz):
1823 in_a = FPOp(width)
1824 in_b = FPOp(width)
1825 in_a.name = "in_a_%d" % i
1826 in_b.name = "in_b_%d" % i
1827 rs.append((in_a, in_b))
1828 self.rs = Array(rs)
1829
1830 res = []
1831 for i in range(rs_sz):
1832 out_z = FPOp(width)
1833 out_z.name = "out_z_%d" % i
1834 res.append(out_z)
1835 self.res = Array(res)
1836
1837 self.states = []
1838
1839 def add_state(self, state):
1840 self.states.append(state)
1841 return state
1842
1843 def get_fragment(self, platform=None):
1844 """ creates the HDL code-fragment for FPAdd
1845 """
1846 m = Module()
1847 m.submodules += self.rs
1848
1849 in_a = self.rs[0][0]
1850 in_b = self.rs[0][1]
1851
1852 out_z = FPOp(self.width)
1853 out_mid = Signal(self.id_wid, reset_less=True)
1854 m.submodules.out_z = out_z
1855
1856 geta = self.add_state(FPGetOp("get_a", "get_b",
1857 in_a, self.width))
1858 geta.setup(m, in_a)
1859 a = geta.out_op
1860
1861 getb = self.add_state(FPGetOp("get_b", "fpadd",
1862 in_b, self.width))
1863 getb.setup(m, in_b)
1864 b = getb.out_op
1865
1866 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1867 ab = self.add_state(ab)
1868 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1869 out_z, out_mid)
1870
1871 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1872 out_mid, "get_a"))
1873
1874 with m.FSM() as fsm:
1875
1876 for state in self.states:
1877 with m.State(state.state_from):
1878 state.action(m)
1879
1880 return m
1881
1882
1883 if __name__ == "__main__":
1884 if True:
1885 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1886 main(alu, ports=alu.rs[0][0].ports() + \
1887 alu.rs[0][1].ports() + \
1888 alu.res[0].ports() + \
1889 [alu.ids.in_mid, alu.ids.out_mid])
1890 else:
1891 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1892 main(alu, ports=[alu.in_a, alu.in_b] + \
1893 alu.in_t.ports() + \
1894 alu.out_z.ports() + \
1895 [alu.in_mid, alu.out_mid])
1896
1897
1898 # works... but don't use, just do "python fname.py convert -t v"
1899 #print (verilog.convert(alu, ports=[
1900 # ports=alu.in_a.ports() + \
1901 # alu.in_b.ports() + \
1902 # alu.out_z.ports())