1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Mux
6 from nmigen
.lib
.coding
import PriorityEncoder
7 from nmigen
.cli
import main
, verilog
9 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
10 from fpbase
import FPNumShiftMultiRight
12 class FPState(FPBase
):
13 def __init__(self
, state_from
):
14 self
.state_from
= state_from
16 def set_inputs(self
, inputs
):
18 for k
,v
in inputs
.items():
21 def set_outputs(self
, outputs
):
22 self
.outputs
= outputs
23 for k
,v
in outputs
.items():
28 def __init__(self
, width
):
29 self
.in_op
= FPOp(width
)
30 self
.out_op
= FPNumIn(self
.in_op
, width
)
31 self
.out_decode
= Signal(reset_less
=True)
33 def setup(self
, m
, in_op
, out_op
, out_decode
):
34 """ links module to inputs and outputs
36 m
.d
.comb
+= self
.in_op
.copy(in_op
)
37 m
.d
.comb
+= out_op
.v
.eq(self
.out_op
.v
)
38 m
.d
.comb
+= out_decode
.eq(self
.out_decode
)
40 def elaborate(self
, platform
):
42 m
.d
.comb
+= self
.out_decode
.eq((self
.in_op
.ack
) & (self
.in_op
.stb
))
43 #m.submodules.get_op_in = self.in_op
44 m
.submodules
.get_op_out
= self
.out_op
45 with m
.If(self
.out_decode
):
47 self
.out_op
.decode(self
.in_op
.v
),
52 class FPGetOp(FPState
):
56 def __init__(self
, in_state
, out_state
, in_op
, width
):
57 FPState
.__init
__(self
, in_state
)
58 self
.out_state
= out_state
59 self
.mod
= FPGetOpMod(width
)
61 self
.out_op
= FPNumIn(in_op
, width
)
62 self
.out_decode
= Signal(reset_less
=True)
65 with m
.If(self
.out_decode
):
66 m
.next
= self
.out_state
69 self
.out_op
.copy(self
.mod
.out_op
)
72 m
.d
.sync
+= self
.in_op
.ack
.eq(1)
75 class FPGetOpB(FPState
):
79 def __init__(self
, in_b
, width
):
80 FPState
.__init
__(self
, "get_b")
82 self
.b
= FPNumIn(self
.in_b
, width
)
85 self
.get_op(m
, self
.in_b
, self
.b
, "special_cases")
88 class FPAddSpecialCasesMod
:
89 """ special cases: NaNs, infs, zeros, denormalised
90 NOTE: some of these are unique to add. see "Special Operations"
91 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
94 def __init__(self
, width
):
95 self
.in_a
= FPNumBase(width
)
96 self
.in_b
= FPNumBase(width
)
97 self
.out_z
= FPNumOut(width
, False)
98 self
.out_do_z
= Signal(reset_less
=True)
100 def setup(self
, m
, in_a
, in_b
, out_z
, out_do_z
):
101 """ links module to inputs and outputs
103 m
.d
.comb
+= self
.in_a
.copy(in_a
)
104 m
.d
.comb
+= self
.in_b
.copy(in_b
)
105 #m.d.comb += out_z.v.eq(self.out_z.v)
106 m
.d
.comb
+= out_do_z
.eq(self
.out_do_z
)
108 def elaborate(self
, platform
):
111 m
.submodules
.sc_in_a
= self
.in_a
112 m
.submodules
.sc_in_b
= self
.in_b
113 m
.submodules
.sc_out_z
= self
.out_z
116 m
.d
.comb
+= s_nomatch
.eq(self
.in_a
.s
!= self
.in_b
.s
)
119 m
.d
.comb
+= m_match
.eq(self
.in_a
.m
== self
.in_b
.m
)
121 # if a is NaN or b is NaN return NaN
122 with m
.If(self
.in_a
.is_nan | self
.in_b
.is_nan
):
123 m
.d
.comb
+= self
.out_do_z
.eq(1)
124 m
.d
.comb
+= self
.out_z
.nan(0)
126 # XXX WEIRDNESS for FP16 non-canonical NaN handling
129 ## if a is zero and b is NaN return -b
130 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
131 # m.d.comb += self.out_do_z.eq(1)
132 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
134 ## if b is zero and a is NaN return -a
135 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
136 # m.d.comb += self.out_do_z.eq(1)
137 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
139 ## if a is -zero and b is NaN return -b
140 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
141 # m.d.comb += self.out_do_z.eq(1)
142 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
144 ## if b is -zero and a is NaN return -a
145 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
146 # m.d.comb += self.out_do_z.eq(1)
147 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
149 # if a is inf return inf (or NaN)
150 with m
.Elif(self
.in_a
.is_inf
):
151 m
.d
.comb
+= self
.out_do_z
.eq(1)
152 m
.d
.comb
+= self
.out_z
.inf(self
.in_a
.s
)
153 # if a is inf and signs don't match return NaN
154 with m
.If(self
.in_b
.exp_128
& s_nomatch
):
155 m
.d
.comb
+= self
.out_z
.nan(0)
157 # if b is inf return inf
158 with m
.Elif(self
.in_b
.is_inf
):
159 m
.d
.comb
+= self
.out_do_z
.eq(1)
160 m
.d
.comb
+= self
.out_z
.inf(self
.in_b
.s
)
162 # if a is zero and b zero return signed-a/b
163 with m
.Elif(self
.in_a
.is_zero
& self
.in_b
.is_zero
):
164 m
.d
.comb
+= self
.out_do_z
.eq(1)
165 m
.d
.comb
+= self
.out_z
.create(self
.in_a
.s
& self
.in_b
.s
,
169 # if a is zero return b
170 with m
.Elif(self
.in_a
.is_zero
):
171 m
.d
.comb
+= self
.out_do_z
.eq(1)
172 m
.d
.comb
+= self
.out_z
.create(self
.in_b
.s
, self
.in_b
.e
,
175 # if b is zero return a
176 with m
.Elif(self
.in_b
.is_zero
):
177 m
.d
.comb
+= self
.out_do_z
.eq(1)
178 m
.d
.comb
+= self
.out_z
.create(self
.in_a
.s
, self
.in_a
.e
,
181 # if a equal to -b return zero (+ve zero)
182 with m
.Elif(s_nomatch
& m_match
& (self
.in_a
.e
== self
.in_b
.e
)):
183 m
.d
.comb
+= self
.out_do_z
.eq(1)
184 m
.d
.comb
+= self
.out_z
.zero(0)
186 # Denormalised Number checks
188 m
.d
.comb
+= self
.out_do_z
.eq(0)
193 class FPAddSpecialCases(FPState
):
194 """ special cases: NaNs, infs, zeros, denormalised
195 NOTE: some of these are unique to add. see "Special Operations"
196 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
199 def __init__(self
, width
):
200 FPState
.__init
__(self
, "special_cases")
201 self
.mod
= FPAddSpecialCasesMod(width
)
202 self
.out_z
= FPNumOut(width
, False)
203 self
.out_do_z
= Signal(reset_less
=True)
206 with m
.If(self
.out_do_z
):
207 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
) # only take the output
210 m
.next
= "denormalise"
213 class FPAddDeNormMod(FPState
):
215 def __init__(self
, width
):
216 self
.in_a
= FPNumBase(width
)
217 self
.in_b
= FPNumBase(width
)
218 self
.out_a
= FPNumBase(width
)
219 self
.out_b
= FPNumBase(width
)
221 def setup(self
, m
, in_a
, in_b
, out_a
, out_b
):
222 """ links module to inputs and outputs
224 m
.d
.comb
+= self
.in_a
.copy(in_a
)
225 m
.d
.comb
+= self
.in_b
.copy(in_b
)
226 m
.d
.comb
+= out_a
.copy(self
.out_a
)
227 m
.d
.comb
+= out_b
.copy(self
.out_b
)
229 def elaborate(self
, platform
):
231 m
.submodules
.denorm_in_a
= self
.in_a
232 m
.submodules
.denorm_in_b
= self
.in_b
233 m
.submodules
.denorm_out_a
= self
.out_a
234 m
.submodules
.denorm_out_b
= self
.out_b
235 # hmmm, don't like repeating identical code
236 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
237 with m
.If(self
.in_a
.exp_n127
):
238 m
.d
.comb
+= self
.out_a
.e
.eq(self
.in_a
.N126
) # limit a exponent
240 m
.d
.comb
+= self
.out_a
.m
[-1].eq(1) # set top mantissa bit
242 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
243 with m
.If(self
.in_b
.exp_n127
):
244 m
.d
.comb
+= self
.out_b
.e
.eq(self
.in_b
.N126
) # limit a exponent
246 m
.d
.comb
+= self
.out_b
.m
[-1].eq(1) # set top mantissa bit
251 class FPAddDeNorm(FPState
):
253 def __init__(self
, width
):
254 FPState
.__init
__(self
, "denormalise")
255 self
.mod
= FPAddDeNormMod(width
)
256 self
.out_a
= FPNumBase(width
)
257 self
.out_b
= FPNumBase(width
)
260 # Denormalised Number checks
262 m
.d
.sync
+= self
.a
.copy(self
.out_a
)
263 m
.d
.sync
+= self
.b
.copy(self
.out_b
)
266 class FPAddAlignMultiMod(FPState
):
268 def __init__(self
, width
):
269 self
.in_a
= FPNumBase(width
)
270 self
.in_b
= FPNumBase(width
)
271 self
.out_a
= FPNumIn(None, width
)
272 self
.out_b
= FPNumIn(None, width
)
273 self
.exp_eq
= Signal(reset_less
=True)
275 def setup(self
, m
, in_a
, in_b
, out_a
, out_b
, exp_eq
):
276 """ links module to inputs and outputs
278 m
.d
.comb
+= self
.in_a
.copy(in_a
)
279 m
.d
.comb
+= self
.in_b
.copy(in_b
)
280 m
.d
.comb
+= out_a
.copy(self
.out_a
)
281 m
.d
.comb
+= out_b
.copy(self
.out_b
)
282 m
.d
.comb
+= exp_eq
.eq(self
.exp_eq
)
284 def elaborate(self
, platform
):
285 # This one however (single-cycle) will do the shift
290 #m.submodules.align_in_a = self.in_a
291 #m.submodules.align_in_b = self.in_b
292 m
.submodules
.align_out_a
= self
.out_a
293 m
.submodules
.align_out_b
= self
.out_b
295 # NOTE: this does *not* do single-cycle multi-shifting,
296 # it *STAYS* in the align state until exponents match
298 # exponent of a greater than b: shift b down
299 m
.d
.comb
+= self
.exp_eq
.eq(0)
300 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
301 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
302 agtb
= Signal(reset_less
=True)
303 altb
= Signal(reset_less
=True)
304 m
.d
.comb
+= agtb
.eq(self
.in_a
.e
> self
.in_b
.e
)
305 m
.d
.comb
+= altb
.eq(self
.in_a
.e
< self
.in_b
.e
)
307 m
.d
.comb
+= self
.out_b
.shift_down(self
.in_b
)
308 # exponent of b greater than a: shift a down
310 m
.d
.comb
+= self
.out_a
.shift_down(self
.in_a
)
311 # exponents equal: move to next stage.
313 m
.d
.comb
+= self
.exp_eq
.eq(1)
317 class FPAddAlignMulti(FPState
):
319 def __init__(self
, width
):
320 FPState
.__init
__(self
, "align")
321 self
.mod
= FPAddAlignMultiMod(width
)
322 self
.out_a
= FPNumIn(None, width
)
323 self
.out_b
= FPNumIn(None, width
)
324 self
.exp_eq
= Signal(reset_less
=True)
327 m
.d
.sync
+= self
.a
.copy(self
.out_a
)
328 m
.d
.sync
+= self
.b
.copy(self
.out_b
)
329 with m
.If(self
.exp_eq
):
333 class FPAddAlignSingleMod
:
335 def __init__(self
, width
):
336 self
.in_a
= FPNumBase(width
)
337 self
.in_b
= FPNumBase(width
)
338 self
.out_a
= FPNumIn(None, width
)
339 self
.out_b
= FPNumIn(None, width
)
340 #self.out_a = FPNumBase(width)
341 #self.out_b = FPNumBase(width)
343 def setup(self
, m
, in_a
, in_b
, out_a
, out_b
):
344 """ links module to inputs and outputs
346 m
.d
.comb
+= self
.in_a
.copy(in_a
)
347 m
.d
.comb
+= self
.in_b
.copy(in_b
)
348 m
.d
.comb
+= out_a
.copy(self
.out_a
)
349 m
.d
.comb
+= out_b
.copy(self
.out_b
)
351 def elaborate(self
, platform
):
352 # This one however (single-cycle) will do the shift
357 m
.submodules
.align_in_a
= self
.in_a
358 m
.submodules
.align_in_b
= self
.in_b
359 m
.submodules
.align_out_a
= self
.out_a
360 m
.submodules
.align_out_b
= self
.out_b
362 # XXX TODO: the shifter used here is quite expensive
363 # having only one would be better
365 ediff
= Signal((len(self
.in_a
.e
), True), reset_less
=True)
366 ediffr
= Signal((len(self
.in_a
.e
), True), reset_less
=True)
368 m
.d
.comb
+= ediff
.eq(self
.in_a
.e
- self
.in_b
.e
)
369 m
.d
.comb
+= ediffr
.eq(self
.in_b
.e
- self
.in_a
.e
)
370 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
371 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
372 with m
.If(ediff
> 0):
373 m
.d
.comb
+= self
.out_b
.shift_down_multi(ediff
, self
.in_b
)
374 # exponent of b greater than a: shift a down
375 with m
.Elif(ediff
< 0):
376 m
.d
.comb
+= self
.out_a
.shift_down_multi(ediffr
, self
.in_a
)
380 class FPAddAlignSingle(FPState
):
382 def __init__(self
, width
):
383 FPState
.__init
__(self
, "align")
384 self
.mod
= FPAddAlignSingleMod(width
)
385 self
.out_a
= FPNumIn(None, width
)
386 self
.out_b
= FPNumIn(None, width
)
389 m
.d
.sync
+= self
.a
.copy(self
.out_a
)
390 m
.d
.sync
+= self
.b
.copy(self
.out_b
)
394 class FPAddStage0Mod
:
396 def __init__(self
, width
):
397 self
.in_a
= FPNumBase(width
)
398 self
.in_b
= FPNumBase(width
)
399 self
.in_z
= FPNumBase(width
, False)
400 self
.out_z
= FPNumBase(width
, False)
401 self
.out_tot
= Signal(self
.out_z
.m_width
+ 4, reset_less
=True)
403 def elaborate(self
, platform
):
405 m
.submodules
.add0_in_a
= self
.in_a
406 m
.submodules
.add0_in_b
= self
.in_b
407 m
.submodules
.add0_out_z
= self
.out_z
409 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_a
.e
)
411 # store intermediate tests (and zero-extended mantissas)
412 seq
= Signal(reset_less
=True)
413 mge
= Signal(reset_less
=True)
414 am0
= Signal(len(self
.in_a
.m
)+1, reset_less
=True)
415 bm0
= Signal(len(self
.in_b
.m
)+1, reset_less
=True)
416 m
.d
.comb
+= [seq
.eq(self
.in_a
.s
== self
.in_b
.s
),
417 mge
.eq(self
.in_a
.m
>= self
.in_b
.m
),
418 am0
.eq(Cat(self
.in_a
.m
, 0)),
419 bm0
.eq(Cat(self
.in_b
.m
, 0))
421 # same-sign (both negative or both positive) add mantissas
424 self
.out_tot
.eq(am0
+ bm0
),
425 self
.out_z
.s
.eq(self
.in_a
.s
)
427 # a mantissa greater than b, use a
430 self
.out_tot
.eq(am0
- bm0
),
431 self
.out_z
.s
.eq(self
.in_a
.s
)
433 # b mantissa greater than a, use b
436 self
.out_tot
.eq(bm0
- am0
),
437 self
.out_z
.s
.eq(self
.in_b
.s
)
442 class FPAddStage0(FPState
):
443 """ First stage of add. covers same-sign (add) and subtract
444 special-casing when mantissas are greater or equal, to
445 give greatest accuracy.
448 def __init__(self
, width
):
449 FPState
.__init
__(self
, "add_0")
450 self
.mod
= FPAddStage0Mod(width
)
451 self
.out_z
= FPNumBase(width
, False)
452 self
.out_tot
= Signal(self
.out_z
.m_width
+ 4, reset_less
=True)
454 def setup(self
, m
, in_a
, in_b
):
455 """ links module to inputs and outputs
457 m
.submodules
.add0
= self
.mod
459 m
.d
.comb
+= self
.mod
.in_a
.copy(in_a
)
460 m
.d
.comb
+= self
.mod
.in_b
.copy(in_b
)
464 # NOTE: these could be done as combinatorial (merge add0+add1)
465 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
466 m
.d
.sync
+= self
.out_tot
.eq(self
.mod
.out_tot
)
469 class FPAddStage1Mod(FPState
):
470 """ Second stage of add: preparation for normalisation.
471 detects when tot sum is too big (tot[27] is kinda a carry bit)
474 def __init__(self
, width
):
475 self
.out_norm
= Signal(reset_less
=True)
476 self
.in_z
= FPNumBase(width
, False)
477 self
.in_tot
= Signal(self
.in_z
.m_width
+ 4, reset_less
=True)
478 self
.out_z
= FPNumBase(width
, False)
479 self
.out_of
= Overflow()
481 def elaborate(self
, platform
):
483 #m.submodules.norm1_in_overflow = self.in_of
484 #m.submodules.norm1_out_overflow = self.out_of
485 #m.submodules.norm1_in_z = self.in_z
486 #m.submodules.norm1_out_z = self.out_z
487 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
488 # tot[27] gets set when the sum overflows. shift result down
489 with m
.If(self
.in_tot
[-1]):
491 self
.out_z
.m
.eq(self
.in_tot
[4:]),
492 self
.out_of
.m0
.eq(self
.in_tot
[4]),
493 self
.out_of
.guard
.eq(self
.in_tot
[3]),
494 self
.out_of
.round_bit
.eq(self
.in_tot
[2]),
495 self
.out_of
.sticky
.eq(self
.in_tot
[1] | self
.in_tot
[0]),
496 self
.out_z
.e
.eq(self
.in_z
.e
+ 1)
501 self
.out_z
.m
.eq(self
.in_tot
[3:]),
502 self
.out_of
.m0
.eq(self
.in_tot
[3]),
503 self
.out_of
.guard
.eq(self
.in_tot
[2]),
504 self
.out_of
.round_bit
.eq(self
.in_tot
[1]),
505 self
.out_of
.sticky
.eq(self
.in_tot
[0])
510 class FPAddStage1(FPState
):
512 def __init__(self
, width
):
513 FPState
.__init
__(self
, "add_1")
514 self
.mod
= FPAddStage1Mod(width
)
515 self
.out_z
= FPNumBase(width
, False)
516 self
.out_of
= Overflow()
517 self
.norm_stb
= Signal()
519 def setup(self
, m
, in_tot
, in_z
):
520 """ links module to inputs and outputs
522 m
.submodules
.add1
= self
.mod
524 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
525 m
.d
.comb
+= self
.mod
.in_tot
.eq(in_tot
)
527 m
.d
.sync
+= self
.norm_stb
.eq(0) # sets to zero when not in add1 state
530 m
.submodules
.add1_out_overflow
= self
.out_of
531 m
.d
.sync
+= self
.out_of
.copy(self
.mod
.out_of
)
532 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
533 m
.d
.sync
+= self
.norm_stb
.eq(1)
534 m
.next
= "normalise_1"
539 def __init__(self
, width
, single_cycle
=True):
540 self
.single_cycle
= single_cycle
542 self
.in_select
= Signal(reset_less
=True)
543 self
.out_norm
= Signal(reset_less
=True)
544 self
.in_z
= FPNumBase(width
, False)
545 self
.in_of
= Overflow()
546 self
.temp_z
= FPNumBase(width
, False)
547 self
.temp_of
= Overflow()
548 self
.out_z
= FPNumBase(width
, False)
549 self
.out_of
= Overflow()
551 def elaborate(self
, platform
):
554 mwid
= self
.out_z
.m_width
+2
555 pe
= PriorityEncoder(mwid
)
556 m
.submodules
.norm_pe
= pe
558 m
.submodules
.norm1_out_z
= self
.out_z
559 m
.submodules
.norm1_out_overflow
= self
.out_of
560 m
.submodules
.norm1_temp_z
= self
.temp_z
561 m
.submodules
.norm1_temp_of
= self
.temp_of
562 m
.submodules
.norm1_in_z
= self
.in_z
563 m
.submodules
.norm1_in_overflow
= self
.in_of
565 in_z
= FPNumBase(self
.width
, False)
567 m
.submodules
.norm1_insel_z
= in_z
568 m
.submodules
.norm1_insel_overflow
= in_of
570 ediff_n126
= Signal((len(in_z
.e
), True), reset_less
=True)
571 smr
= FPNumShiftMultiRight(in_z
, ediff_n126
, in_z
.m_width
+2)
572 m
.submodules
.norm1_smr
= smr
574 # select which of temp or in z/of to use
575 with m
.If(self
.in_select
):
576 m
.d
.comb
+= in_z
.copy(self
.in_z
)
577 m
.d
.comb
+= in_of
.copy(self
.in_of
)
579 m
.d
.comb
+= in_z
.copy(self
.temp_z
)
580 m
.d
.comb
+= in_of
.copy(self
.temp_of
)
581 # initialise out from in (overridden below)
582 m
.d
.comb
+= self
.out_z
.copy(in_z
)
583 m
.d
.comb
+= self
.out_of
.copy(in_of
)
584 # normalisation increase/decrease conditions
585 decrease
= Signal(reset_less
=True)
586 increase
= Signal(reset_less
=True)
587 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
& in_z
.exp_gt_n126
)
588 m
.d
.comb
+= increase
.eq(in_z
.exp_lt_n126
)
589 if not self
.single_cycle
:
590 m
.d
.comb
+= self
.out_norm
.eq(decrease | increase
) # loop-end
592 m
.d
.comb
+= self
.out_norm
.eq(increase
) # loop-end condition
595 if not self
.single_cycle
:
597 self
.out_z
.e
.eq(in_z
.e
- 1), # DECREASE exponent
598 self
.out_z
.m
.eq(in_z
.m
<< 1), # shift mantissa UP
599 self
.out_z
.m
[0].eq(in_of
.guard
), # steal guard (was tot[2])
600 self
.out_of
.guard
.eq(in_of
.round_bit
), # round (was tot[1])
601 self
.out_of
.round_bit
.eq(0), # reset round bit
602 self
.out_of
.m0
.eq(in_of
.guard
),
605 # *sigh* not entirely obvious: count leading zeros (clz)
606 # with a PriorityEncoder: to find from the MSB
607 # we reverse the order of the bits.
608 temp_m
= Signal(mwid
, reset_less
=True)
609 temp_s
= Signal(mwid
+1, reset_less
=True)
610 clz
= Signal((len(in_z
.e
), True), reset_less
=True)
611 # make sure that the amount to decrease by does NOT
612 # go below the minimum non-INF/NaN exponent
613 limclz
= Mux(in_z
.e
- pe
.o
- in_z
.N126
> 0, pe
.o
,
616 # cat round and guard bits back into the mantissa
617 temp_m
.eq(Cat(in_of
.round_bit
,
620 pe
.i
.eq(temp_m
[::-1]), # inverted
621 clz
.eq(limclz
), # count zeros from MSB down
622 temp_s
.eq(temp_m
<< clz
), # shift mantissa UP
623 self
.out_z
.e
.eq(in_z
.e
- clz
), # DECREASE exponent
624 self
.out_z
.m
.eq(temp_s
[2:]), # exclude bits 0&1
625 self
.out_of
.m0
.eq(temp_s
[2]), # copy of mantissa[0]
626 # overflow in bits 0..1: got shifted too (leave sticky)
627 self
.out_of
.guard
.eq(temp_s
[1]), # guard
628 self
.out_of
.round_bit
.eq(temp_s
[0]), # round
631 with m
.Elif(increase
):
632 if self
.single_cycle
:
634 self
.out_z
.e
.eq(in_z
.e
+ 1), # INCREASE exponent
635 self
.out_z
.m
.eq(in_z
.m
>> 1), # shift mantissa DOWN
636 self
.out_of
.guard
.eq(in_z
.m
[0]),
637 self
.out_of
.m0
.eq(in_z
.m
[1]),
638 self
.out_of
.round_bit
.eq(in_of
.guard
),
639 self
.out_of
.sticky
.eq(in_of
.sticky | in_of
.round_bit
)
643 ediff_n126
.eq(in_z
.N126
- in_z
.e
),
649 class FPNorm1(FPState
):
651 def __init__(self
, width
):
652 FPState
.__init
__(self
, "normalise_1")
653 self
.mod
= FPNorm1Mod(width
)
654 self
.stb
= Signal(reset_less
=True)
655 self
.ack
= Signal(reset
=0, reset_less
=True)
656 self
.out_norm
= Signal(reset_less
=True)
657 self
.in_accept
= Signal(reset_less
=True)
658 self
.temp_z
= FPNumBase(width
)
659 self
.temp_of
= Overflow()
660 self
.out_z
= FPNumBase(width
)
661 self
.out_roundz
= Signal(reset_less
=True)
663 def setup(self
, m
, in_z
, in_of
, norm_stb
):
664 """ links module to inputs and outputs
666 m
.submodules
.normalise_1
= self
.mod
668 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
669 m
.d
.comb
+= self
.mod
.in_of
.copy(in_of
)
671 m
.d
.comb
+= self
.mod
.in_select
.eq(self
.in_accept
)
672 m
.d
.comb
+= self
.mod
.temp_z
.copy(self
.temp_z
)
673 m
.d
.comb
+= self
.mod
.temp_of
.copy(self
.temp_of
)
675 m
.d
.comb
+= self
.out_z
.copy(self
.mod
.out_z
)
676 m
.d
.comb
+= self
.out_norm
.eq(self
.mod
.out_norm
)
678 m
.d
.comb
+= self
.stb
.eq(norm_stb
)
679 m
.d
.sync
+= self
.ack
.eq(0) # sets to zero when not in normalise_1 state
683 m
.d
.comb
+= self
.in_accept
.eq((~self
.ack
) & (self
.stb
))
684 m
.d
.sync
+= self
.temp_of
.copy(self
.mod
.out_of
)
685 m
.d
.sync
+= self
.temp_z
.copy(self
.out_z
)
686 with m
.If(self
.out_norm
):
687 with m
.If(self
.in_accept
):
692 m
.d
.sync
+= self
.ack
.eq(0)
694 # normalisation not required (or done).
696 m
.d
.sync
+= self
.ack
.eq(1)
697 m
.d
.sync
+= self
.out_roundz
.eq(self
.mod
.out_of
.roundz
)
702 def __init__(self
, width
):
703 self
.in_roundz
= Signal(reset_less
=True)
704 self
.in_z
= FPNumBase(width
, False)
705 self
.out_z
= FPNumBase(width
, False)
707 def elaborate(self
, platform
):
709 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
710 with m
.If(self
.in_roundz
):
711 m
.d
.comb
+= self
.out_z
.m
.eq(self
.in_z
.m
+ 1) # mantissa rounds up
712 with m
.If(self
.in_z
.m
== self
.in_z
.m1s
): # all 1s
713 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.e
+ 1) # exponent up
717 class FPRound(FPState
):
719 def __init__(self
, width
):
720 FPState
.__init
__(self
, "round")
721 self
.mod
= FPRoundMod(width
)
722 self
.out_z
= FPNumBase(width
)
724 def setup(self
, m
, in_z
, roundz
):
725 """ links module to inputs and outputs
727 m
.submodules
.roundz
= self
.mod
729 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
730 m
.d
.comb
+= self
.mod
.in_roundz
.eq(roundz
)
733 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
734 m
.next
= "corrections"
737 class FPCorrectionsMod
:
739 def __init__(self
, width
):
740 self
.in_z
= FPNumOut(width
, False)
741 self
.out_z
= FPNumOut(width
, False)
743 def elaborate(self
, platform
):
745 m
.submodules
.corr_in_z
= self
.in_z
746 m
.submodules
.corr_out_z
= self
.out_z
747 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
748 with m
.If(self
.in_z
.is_denormalised
):
749 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.N127
)
751 # with m.If(self.in_z.is_overflowed):
752 # m.d.comb += self.out_z.inf(self.in_z.s)
754 # m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
758 class FPCorrections(FPState
):
760 def __init__(self
, width
):
761 FPState
.__init
__(self
, "corrections")
762 self
.mod
= FPCorrectionsMod(width
)
763 self
.out_z
= FPNumBase(width
)
765 def setup(self
, m
, in_z
):
766 """ links module to inputs and outputs
768 m
.submodules
.corrections
= self
.mod
769 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
772 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
778 def __init__(self
, width
):
779 self
.in_z
= FPNumOut(width
, False)
780 self
.out_z
= FPNumOut(width
, False)
782 def elaborate(self
, platform
):
784 m
.submodules
.pack_in_z
= self
.in_z
785 with m
.If(self
.in_z
.is_overflowed
):
786 m
.d
.comb
+= self
.out_z
.inf(self
.in_z
.s
)
788 m
.d
.comb
+= self
.out_z
.create(self
.in_z
.s
, self
.in_z
.e
, self
.in_z
.m
)
792 class FPPack(FPState
):
794 def __init__(self
, width
):
795 FPState
.__init
__(self
, "pack")
796 self
.mod
= FPPackMod(width
)
797 self
.out_z
= FPNumOut(width
, False)
799 def setup(self
, m
, in_z
):
800 """ links module to inputs and outputs
802 m
.submodules
.pack
= self
.mod
803 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
806 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
)
807 m
.next
= "pack_put_z"
810 class FPPutZ(FPState
):
812 def __init__(self
, state
, in_z
, out_z
):
813 FPState
.__init
__(self
, state
)
819 self
.out_z
.v
.eq(self
.in_z
.v
)
821 with m
.If(self
.out_z
.stb
& self
.out_z
.ack
):
822 m
.d
.sync
+= self
.out_z
.stb
.eq(0)
825 m
.d
.sync
+= self
.out_z
.stb
.eq(1)
830 def __init__(self
, width
, single_cycle
=False):
832 self
.single_cycle
= single_cycle
834 self
.in_a
= FPOp(width
)
835 self
.in_b
= FPOp(width
)
836 self
.out_z
= FPOp(width
)
840 def add_state(self
, state
):
841 self
.states
.append(state
)
844 def get_fragment(self
, platform
=None):
845 """ creates the HDL code-fragment for FPAdd
848 m
.submodules
.in_a
= self
.in_a
849 m
.submodules
.in_b
= self
.in_b
850 m
.submodules
.out_z
= self
.out_z
852 geta
= self
.add_state(FPGetOp("get_a", "get_b",
853 self
.in_a
, self
.width
))
855 geta
.mod
.setup(m
, self
.in_a
, geta
.out_op
, geta
.out_decode
)
856 m
.submodules
.get_a
= geta
.mod
858 getb
= self
.add_state(FPGetOp("get_b", "special_cases",
859 self
.in_b
, self
.width
))
861 getb
.mod
.setup(m
, self
.in_b
, getb
.out_op
, getb
.out_decode
)
862 m
.submodules
.get_b
= getb
.mod
864 sc
= self
.add_state(FPAddSpecialCases(self
.width
))
865 sc
.mod
.setup(m
, a
, b
, sc
.out_z
, sc
.out_do_z
)
866 m
.submodules
.specialcases
= sc
.mod
868 dn
= self
.add_state(FPAddDeNorm(self
.width
))
869 dn
.set_inputs({"a": a
, "b": b
})
870 #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
871 dn
.mod
.setup(m
, a
, b
, dn
.out_a
, dn
.out_b
)
872 m
.submodules
.denormalise
= dn
.mod
874 if self
.single_cycle
:
875 alm
= self
.add_state(FPAddAlignSingle(self
.width
))
876 alm
.set_inputs({"a": a
, "b": b
})
877 alm
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
878 alm
.mod
.setup(m
, a
, b
, alm
.out_a
, alm
.out_b
)
880 alm
= self
.add_state(FPAddAlignMulti(self
.width
))
881 alm
.set_inputs({"a": a
, "b": b
})
882 #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
883 alm
.mod
.setup(m
, a
, b
, alm
.out_a
, alm
.out_b
, alm
.exp_eq
)
884 m
.submodules
.align
= alm
.mod
886 add0
= self
.add_state(FPAddStage0(self
.width
))
887 add0
.setup(m
, alm
.out_a
, alm
.out_b
)
889 add1
= self
.add_state(FPAddStage1(self
.width
))
890 add1
.setup(m
, add0
.out_tot
, add0
.out_z
)
892 n1
= self
.add_state(FPNorm1(self
.width
))
893 n1
.setup(m
, add1
.out_z
, add1
.out_of
, add1
.norm_stb
)
895 rn
= self
.add_state(FPRound(self
.width
))
896 rn
.setup(m
, n1
.out_z
, n1
.out_roundz
)
898 cor
= self
.add_state(FPCorrections(self
.width
))
899 cor
.setup(m
, rn
.out_z
)
901 pa
= self
.add_state(FPPack(self
.width
))
902 pa
.setup(m
, cor
.out_z
)
904 ppz
= self
.add_state(FPPutZ("pack_put_z", pa
.out_z
, self
.out_z
))
906 pz
= self
.add_state(FPPutZ("put_z", sc
.out_z
, self
.out_z
))
910 for state
in self
.states
:
911 with m
.State(state
.state_from
):
917 if __name__
== "__main__":
918 alu
= FPADD(width
=32, single_cycle
=True)
919 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
922 # works... but don't use, just do "python fname.py convert -t v"
923 #print (verilog.convert(alu, ports=[
924 # ports=alu.in_a.ports() + \
925 # alu.in_b.ports() + \