1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
6 from nmigen
.cli
import main
, verilog
8 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
11 class FPState(FPBase
):
12 def __init__(self
, state_from
):
13 self
.state_from
= state_from
15 def set_inputs(self
, inputs
):
17 for k
,v
in inputs
.items():
20 def set_outputs(self
, outputs
):
21 self
.outputs
= outputs
22 for k
,v
in outputs
.items():
26 class FPGetOpA(FPState
):
30 def __init__(self
, in_a
, width
):
31 FPState
.__init
__(self
, "get_a")
33 self
.a
= FPNumIn(in_a
, width
)
36 self
.get_op(m
, self
.in_a
, self
.a
, "get_b")
39 class FPGetOpB(FPState
):
44 self
.get_op(m
, self
.in_b
, self
.b
, "special_cases")
47 class FPAddSpecialCases(FPState
):
48 """ special cases: NaNs, infs, zeros, denormalised
49 NOTE: some of these are unique to add. see "Special Operations"
50 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
55 m
.d
.comb
+= s_nomatch
.eq(self
.a
.s
!= self
.b
.s
)
58 m
.d
.comb
+= m_match
.eq(self
.a
.m
== self
.b
.m
)
60 # if a is NaN or b is NaN return NaN
61 with m
.If(self
.a
.is_nan | self
.b
.is_nan
):
63 m
.d
.sync
+= self
.z
.nan(1)
65 # XXX WEIRDNESS for FP16 non-canonical NaN handling
68 ## if a is zero and b is NaN return -b
69 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
71 # m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
73 ## if b is zero and a is NaN return -a
74 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
76 # m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
78 ## if a is -zero and b is NaN return -b
79 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
81 # m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
83 ## if b is -zero and a is NaN return -a
84 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
86 # m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
88 # if a is inf return inf (or NaN)
89 with m
.Elif(self
.a
.is_inf
):
91 m
.d
.sync
+= self
.z
.inf(self
.a
.s
)
92 # if a is inf and signs don't match return NaN
93 with m
.If(self
.b
.exp_128
& s_nomatch
):
94 m
.d
.sync
+= self
.z
.nan(1)
96 # if b is inf return inf
97 with m
.Elif(self
.b
.is_inf
):
99 m
.d
.sync
+= self
.z
.inf(self
.b
.s
)
101 # if a is zero and b zero return signed-a/b
102 with m
.Elif(self
.a
.is_zero
& self
.b
.is_zero
):
104 m
.d
.sync
+= self
.z
.create(self
.a
.s
& self
.b
.s
, self
.b
.e
,
107 # if a is zero return b
108 with m
.Elif(self
.a
.is_zero
):
110 m
.d
.sync
+= self
.z
.create(self
.b
.s
, self
.b
.e
, self
.b
.m
[3:-1])
112 # if b is zero return a
113 with m
.Elif(self
.b
.is_zero
):
115 m
.d
.sync
+= self
.z
.create(self
.a
.s
, self
.a
.e
, self
.a
.m
[3:-1])
117 # if a equal to -b return zero (+ve zero)
118 with m
.Elif(s_nomatch
& m_match
& (self
.a
.e
== self
.b
.e
)):
120 m
.d
.sync
+= self
.z
.zero(0)
122 # Denormalised Number checks
124 m
.next
= "denormalise"
127 class FPAddDeNorm(FPState
):
130 # Denormalised Number checks
132 self
.denormalise(m
, self
.a
)
133 self
.denormalise(m
, self
.b
)
136 class FPAddAlignMulti(FPState
):
139 # NOTE: this does *not* do single-cycle multi-shifting,
140 # it *STAYS* in the align state until exponents match
142 # exponent of a greater than b: shift b down
143 with m
.If(self
.a
.e
> self
.b
.e
):
144 m
.d
.sync
+= self
.b
.shift_down()
145 # exponent of b greater than a: shift a down
146 with m
.Elif(self
.a
.e
< self
.b
.e
):
147 m
.d
.sync
+= self
.a
.shift_down()
148 # exponents equal: move to next stage.
153 class FPAddAlignSingle(FPState
):
156 # This one however (single-cycle) will do the shift
159 # XXX TODO: the shifter used here is quite expensive
160 # having only one would be better
162 ediff
= Signal((len(self
.a
.e
), True), reset_less
=True)
163 ediffr
= Signal((len(self
.a
.e
), True), reset_less
=True)
164 m
.d
.comb
+= ediff
.eq(self
.a
.e
- self
.b
.e
)
165 m
.d
.comb
+= ediffr
.eq(self
.b
.e
- self
.a
.e
)
166 with m
.If(ediff
> 0):
167 m
.d
.sync
+= self
.b
.shift_down_multi(ediff
)
168 # exponent of b greater than a: shift a down
169 with m
.Elif(ediff
< 0):
170 m
.d
.sync
+= self
.a
.shift_down_multi(ediffr
)
175 class FPAddStage0(FPState
):
176 """ First stage of add. covers same-sign (add) and subtract
177 special-casing when mantissas are greater or equal, to
178 give greatest accuracy.
183 m
.d
.sync
+= self
.z
.e
.eq(self
.a
.e
)
184 # same-sign (both negative or both positive) add mantissas
185 with m
.If(self
.a
.s
== self
.b
.s
):
187 self
.tot
.eq(Cat(self
.a
.m
, 0) + Cat(self
.b
.m
, 0)),
188 self
.z
.s
.eq(self
.a
.s
)
190 # a mantissa greater than b, use a
191 with m
.Elif(self
.a
.m
>= self
.b
.m
):
193 self
.tot
.eq(Cat(self
.a
.m
, 0) - Cat(self
.b
.m
, 0)),
194 self
.z
.s
.eq(self
.a
.s
)
196 # b mantissa greater than a, use b
199 self
.tot
.eq(Cat(self
.b
.m
, 0) - Cat(self
.a
.m
, 0)),
200 self
.z
.s
.eq(self
.b
.s
)
204 class FPAddStage1(FPState
):
205 """ Second stage of add: preparation for normalisation.
206 detects when tot sum is too big (tot[27] is kinda a carry bit)
210 m
.next
= "normalise_1"
211 # tot[27] gets set when the sum overflows. shift result down
212 with m
.If(self
.tot
[-1]):
214 self
.z
.m
.eq(self
.tot
[4:]),
215 self
.of
.m0
.eq(self
.tot
[4]),
216 self
.of
.guard
.eq(self
.tot
[3]),
217 self
.of
.round_bit
.eq(self
.tot
[2]),
218 self
.of
.sticky
.eq(self
.tot
[1] | self
.tot
[0]),
219 self
.z
.e
.eq(self
.z
.e
+ 1)
224 self
.z
.m
.eq(self
.tot
[3:]),
225 self
.of
.m0
.eq(self
.tot
[3]),
226 self
.of
.guard
.eq(self
.tot
[2]),
227 self
.of
.round_bit
.eq(self
.tot
[1]),
228 self
.of
.sticky
.eq(self
.tot
[0])
232 class FPNorm1(FPState
):
235 self
.normalise_1(m
, self
.z
, self
.of
, "normalise_2")
238 class FPNorm2(FPState
):
241 self
.normalise_2(m
, self
.z
, self
.of
, "round")
246 def __init__(self
, width
):
247 self
.in_roundz
= Signal(reset_less
=True)
248 self
.in_z
= FPNumBase(width
, False)
249 self
.out_z
= FPNumBase(width
, False)
251 def setup(self
, m
, in_z
, out_z
, in_of
):
252 """ links module to inputs and outputs
254 m
.d
.comb
+= self
.in_z
.copy(in_z
)
255 m
.d
.comb
+= out_z
.copy(self
.out_z
)
256 m
.d
.comb
+= self
.in_roundz
.eq(in_of
.roundz
)
258 def elaborate(self
, platform
):
260 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
261 with m
.If(self
.in_roundz
):
262 m
.d
.comb
+= self
.out_z
.m
.eq(self
.in_z
.m
+ 1) # mantissa rounds up
263 with m
.If(self
.in_z
.m
== self
.in_z
.m1s
): # all 1s
264 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.e
+ 1) # exponent up
268 class FPRound(FPState
):
270 def __init__(self
, width
):
271 FPState
.__init
__(self
, "round")
272 self
.mod
= FPRoundMod(width
)
273 self
.out_z
= FPNumBase(width
)
276 m
.d
.sync
+= self
.z
.copy(self
.out_z
)
277 m
.next
= "corrections"
280 class FPCorrections(FPState
):
283 self
.corrections(m
, self
.z
, "pack")
286 class FPPack(FPState
):
289 self
.pack(m
, self
.z
, "put_z")
292 class FPPutZ(FPState
):
295 self
.put_z(m
, self
.z
, self
.out_z
, "get_a")
300 def __init__(self
, width
, single_cycle
=False):
302 self
.single_cycle
= single_cycle
304 self
.in_a
= FPOp(width
)
305 self
.in_b
= FPOp(width
)
306 self
.out_z
= FPOp(width
)
310 def add_state(self
, state
):
311 self
.states
.append(state
)
314 def get_fragment(self
, platform
=None):
315 """ creates the HDL code-fragment for FPAdd
320 #a = FPNumIn(self.in_a, self.width)
321 b
= FPNumIn(self
.in_b
, self
.width
)
322 z
= FPNumOut(self
.width
, False)
324 m
.submodules
.fpnum_b
= b
325 m
.submodules
.fpnum_z
= z
328 tot
= Signal(w
, reset_less
=True) # sticky/round/guard, {mantissa} result, 1 overflow
331 m
.submodules
.overflow
= of
333 geta
= self
.add_state(FPGetOpA(self
.in_a
, self
.width
))
334 #geta.set_inputs({"in_a": self.in_a})
335 #geta.set_outputs({"a": a})
337 # XXX m.d.comb += a.v.eq(self.in_a.v) # links in_a to a
338 m
.submodules
.fpnum_a
= a
340 getb
= self
.add_state(FPGetOpB("get_b"))
341 getb
.set_inputs({"in_b": self
.in_b
})
342 getb
.set_outputs({"b": b
})
343 # XXX m.d.comb += b.v.eq(self.in_b.v) # links in_b to b
345 sc
= self
.add_state(FPAddSpecialCases("special_cases"))
346 sc
.set_inputs({"a": a
, "b": b
})
347 sc
.set_outputs({"z": z
})
349 dn
= self
.add_state(FPAddDeNorm("denormalise"))
350 dn
.set_inputs({"a": a
, "b": b
})
351 dn
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
353 if self
.single_cycle
:
354 alm
= self
.add_state(FPAddAlignSingle("align"))
356 alm
= self
.add_state(FPAddAlignMulti("align"))
357 alm
.set_inputs({"a": a
, "b": b
})
358 alm
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
360 add0
= self
.add_state(FPAddStage0("add_0"))
361 add0
.set_inputs({"a": a
, "b": b
})
362 add0
.set_outputs({"z": z
, "tot": tot
})
364 add1
= self
.add_state(FPAddStage1("add_1"))
365 add1
.set_inputs({"tot": tot
, "z": z
}) # Z input passes through
366 add1
.set_outputs({"z": z
, "of": of
}) # XXX Z as output
368 n1
= self
.add_state(FPNorm1("normalise_1"))
369 n1
.set_inputs({"z": z
, "of": of
}) # XXX Z as output
370 n1
.set_outputs({"z": z
}) # XXX Z as output
372 n2
= self
.add_state(FPNorm2("normalise_2"))
373 n2
.set_inputs({"z": z
, "of": of
}) # XXX Z as output
374 n2
.set_outputs({"z": z
}) # XXX Z as output
376 rn
= self
.add_state(FPRound(self
.width
))
377 rn
.set_inputs({"z": z
, "of": of
}) # XXX Z as output
378 rn
.set_outputs({"z": z
}) # XXX Z as output
379 rn
.mod
.setup(m
, z
, rn
.out_z
, of
)
381 m
.submodules
.roundz
= rn
.mod
383 cor
= self
.add_state(FPCorrections("corrections"))
384 cor
.set_inputs({"z": z
}) # XXX Z as output
385 cor
.set_outputs({"z": z
}) # XXX Z as output
387 pa
= self
.add_state(FPPack("pack"))
388 pa
.set_inputs({"z": z
}) # XXX Z as output
389 pa
.set_outputs({"z": z
}) # XXX Z as output
391 pz
= self
.add_state(FPPutZ("put_z"))
392 pz
.set_inputs({"z": z
})
393 pz
.set_outputs({"out_z": self
.out_z
})
397 for state
in self
.states
:
398 with m
.State(state
.state_from
):
404 if __name__
== "__main__":
405 alu
= FPADD(width
=32)
406 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
409 # works... but don't use, just do "python fname.py convert -t v"
410 #print (verilog.convert(alu, ports=[
411 # ports=alu.in_a.ports() + \
412 # alu.in_b.ports() + \