1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
6 from nmigen
.cli
import main
, verilog
8 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
13 def __init__(self
, width
, single_cycle
=False):
16 self
.single_cycle
= single_cycle
18 self
.in_a
= FPOp(width
)
19 self
.in_b
= FPOp(width
)
20 self
.out_z
= FPOp(width
)
22 def get_fragment(self
, platform
=None):
23 """ creates the HDL code-fragment for FPAdd
28 a
= FPNumIn(self
.in_a
, self
.width
)
29 b
= FPNumIn(self
.in_b
, self
.width
)
30 z
= FPNumOut(self
.width
, False)
32 m
.submodules
.fpnum_a
= a
33 m
.submodules
.fpnum_b
= b
34 m
.submodules
.fpnum_z
= z
36 m
.d
.comb
+= a
.v
.eq(self
.in_a
.v
)
37 m
.d
.comb
+= b
.v
.eq(self
.in_b
.v
)
40 tot
= Signal(w
, reset_less
=True) # sticky/round/guard, {mantissa} result, 1 overflow
44 m
.submodules
.overflow
= of
51 with m
.State("get_a"):
52 self
.get_op(m
, self
.in_a
, a
, "get_b")
57 with m
.State("get_b"):
58 self
.get_op(m
, self
.in_b
, b
, "special_cases")
61 # special cases: NaNs, infs, zeros, denormalised
62 # NOTE: some of these are unique to add. see "Special Operations"
63 # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
65 with m
.State("special_cases"):
68 m
.d
.comb
+= s_nomatch
.eq(a
.s
!= b
.s
)
71 m
.d
.comb
+= m_match
.eq(a
.m
== b
.m
)
73 # if a is NaN or b is NaN return NaN
74 with m
.If(a
.is_nan | b
.is_nan
):
78 # XXX WEIRDNESS for FP16 non-canonical NaN handling
81 ## if a is zero and b is NaN return -b
82 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
84 # m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
86 ## if b is zero and a is NaN return -a
87 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
89 # m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
91 ## if a is -zero and b is NaN return -b
92 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
94 # m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
96 ## if b is -zero and a is NaN return -a
97 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
99 # m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
101 # if a is inf return inf (or NaN)
102 with m
.Elif(a
.is_inf
):
104 m
.d
.sync
+= z
.inf(a
.s
)
105 # if a is inf and signs don't match return NaN
106 with m
.If(b
.exp_128
& s_nomatch
):
109 # if b is inf return inf
110 with m
.Elif(b
.is_inf
):
112 m
.d
.sync
+= z
.inf(b
.s
)
114 # if a is zero and b zero return signed-a/b
115 with m
.Elif(a
.is_zero
& b
.is_zero
):
117 m
.d
.sync
+= z
.create(a
.s
& b
.s
, b
.e
, b
.m
[3:-1])
119 # if a is zero return b
120 with m
.Elif(a
.is_zero
):
122 m
.d
.sync
+= z
.create(b
.s
, b
.e
, b
.m
[3:-1])
124 # if b is zero return a
125 with m
.Elif(b
.is_zero
):
127 m
.d
.sync
+= z
.create(a
.s
, a
.e
, a
.m
[3:-1])
129 # if a equal to -b return zero (+ve zero)
130 with m
.Elif(s_nomatch
& m_match
& (a
.e
== b
.e
)):
132 m
.d
.sync
+= z
.zero(0)
134 # Denormalised Number checks
137 self
.denormalise(m
, a
)
138 self
.denormalise(m
, b
)
143 with m
.State("align"):
144 if not self
.single_cycle
:
145 # NOTE: this does *not* do single-cycle multi-shifting,
146 # it *STAYS* in the align state until exponents match
148 # exponent of a greater than b: shift b down
149 with m
.If(a
.e
> b
.e
):
150 m
.d
.sync
+= b
.shift_down()
151 # exponent of b greater than a: shift a down
152 with m
.Elif(a
.e
< b
.e
):
153 m
.d
.sync
+= a
.shift_down()
154 # exponents equal: move to next stage.
158 # This one however (single-cycle) will do the shift
161 # XXX TODO: the shifter used here is quite expensive
162 # having only one would be better
164 ediff
= Signal((len(a
.e
), True), reset_less
=True)
165 ediffr
= Signal((len(a
.e
), True), reset_less
=True)
166 m
.d
.comb
+= ediff
.eq(a
.e
- b
.e
)
167 m
.d
.comb
+= ediffr
.eq(b
.e
- a
.e
)
168 with m
.If(ediff
> 0):
169 m
.d
.sync
+= b
.shift_down_multi(ediff
)
170 # exponent of b greater than a: shift a down
171 with m
.Elif(ediff
< 0):
172 m
.d
.sync
+= a
.shift_down_multi(ediffr
)
177 # First stage of add. covers same-sign (add) and subtract
178 # special-casing when mantissas are greater or equal, to
179 # give greatest accuracy.
181 with m
.State("add_0"):
183 m
.d
.sync
+= z
.e
.eq(a
.e
)
184 # same-sign (both negative or both positive) add mantissas
185 with m
.If(a
.s
== b
.s
):
187 tot
.eq(Cat(a
.m
, 0) + Cat(b
.m
, 0)),
190 # a mantissa greater than b, use a
191 with m
.Elif(a
.m
>= b
.m
):
193 tot
.eq(Cat(a
.m
, 0) - Cat(b
.m
, 0)),
196 # b mantissa greater than a, use b
199 tot
.eq(Cat(b
.m
, 0) - Cat(a
.m
, 0)),
204 # Second stage of add: preparation for normalisation.
205 # detects when tot sum is too big (tot[27] is kinda a carry bit)
207 with m
.State("add_1"):
208 m
.next
= "normalise_1"
209 # tot[27] gets set when the sum overflows. shift result down
215 of
.round_bit
.eq(tot
[2]),
216 of
.sticky
.eq(tot
[1] | tot
[0]),
225 of
.round_bit
.eq(tot
[1]),
230 # First stage of normalisation.
232 with m
.State("normalise_1"):
233 self
.normalise_1(m
, z
, of
, "normalise_2")
236 # Second stage of normalisation.
238 with m
.State("normalise_2"):
239 self
.normalise_2(m
, z
, of
, "round")
244 with m
.State("round"):
245 self
.roundz(m
, z
, of
, "corrections")
250 with m
.State("corrections"):
251 self
.corrections(m
, z
, "pack")
256 with m
.State("pack"):
257 self
.pack(m
, z
, "put_z")
262 with m
.State("put_z"):
263 self
.put_z(m
, z
, self
.out_z
, "get_a")
268 if __name__
== "__main__":
269 alu
= FPADD(width
=32)
270 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
273 # works... but don't use, just do "python fname.py convert -t v"
274 #print (verilog.convert(alu, ports=[
275 # ports=alu.in_a.ports() + \
276 # alu.in_b.ports() + \