1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Const
6 from nmigen
.cli
import main
, verilog
10 """ Floating-point Number Class, variable-width TODO (currently 32-bit)
12 Contains signals for an incoming copy of the value, decoded into
13 sign / exponent / mantissa.
14 Also contains encoding functions, creation and recognition of
15 zero, NaN and inf (all signed)
17 Four extra bits are included in the mantissa: the top bit
18 (m[-1]) is effectively a carry-overflow. The other three are
19 guard (m[2]), round (m[1]), and sticky (m[0])
21 def __init__(self
, width
, m_width
=None):
24 m_width
= width
- 5 # mantissa extra bits (top,guard,round)
25 self
.v
= Signal(width
) # Latched copy of value
26 self
.m
= Signal(m_width
) # Mantissa
27 self
.e
= Signal((10, True)) # Exponent: 10 bits, signed
28 self
.s
= Signal() # Sign bit
30 self
.mzero
= Const(0, (m_width
, False))
31 self
.P127
= Const(127, (10, True))
32 self
.N127
= Const(-127, (10, True))
33 self
.N126
= Const(-126, (10, True))
36 """ decodes a latched value into sign / exponent / mantissa
38 bias is subtracted here, from the exponent. exponent
39 is extended to 10 bits so that subtract 127 is done on
43 return [self
.m
.eq(Cat(0, 0, 0, v
[0:23])), # mantissa
44 self
.e
.eq(v
[23:31] - self
.P127
), # exp (minus bias)
45 self
.s
.eq(v
[31]), # sign
48 def create(self
, s
, e
, m
):
49 """ creates a value from sign / exponent / mantissa
51 bias is added here, to the exponent
54 self
.v
[31].eq(s
), # sign
55 self
.v
[23:31].eq(e
+ self
.P127
), # exp (add on bias)
56 self
.v
[0:23].eq(m
) # mantissa
60 """ shifts a mantissa down by one. exponent is increased to compensate
62 accuracy is lost as a result in the mantissa however there are 3
63 guard bits (the latter of which is the "sticky" bit)
65 return [self
.e
.eq(self
.e
+ 1),
66 self
.m
.eq(Cat(self
.m
[0] | self
.m
[1], self
.m
[1:-5], 0))
70 return self
.create(s
, 0x80, 1<<22)
73 return self
.create(s
, 0x80, 0)
76 return self
.create(s
, -127, 0)
79 return (self
.e
== 128) & (self
.m
!= 0)
82 return (self
.e
== 128) & (self
.m
== 0)
85 return (self
.e
== self
.N127
) & (self
.m
== self
.mzero
)
87 def is_overflowed(self
):
90 def is_denormalised(self
):
91 return (self
.e
== self
.N126
) & (self
.m
[23] == 0)
95 def __init__(self
, width
):
98 self
.in_a
= Signal(width
)
99 self
.in_a_stb
= Signal()
100 self
.in_a_ack
= Signal()
102 self
.in_b
= Signal(width
)
103 self
.in_b_stb
= Signal()
104 self
.in_b_ack
= Signal()
106 self
.out_z
= Signal(width
)
107 self
.out_z_stb
= Signal()
108 self
.out_z_ack
= Signal()
110 def get_fragment(self
, platform
=None):
114 a
= FPNum(self
.width
)
115 b
= FPNum(self
.width
)
116 z
= FPNum(self
.width
, 24)
118 tot
= Signal(28) # sticky/round/guard bits, 23 result, 1 overflow
120 guard
= Signal() # tot[2]
121 round_bit
= Signal() # tot[1]
122 sticky
= Signal() # tot[0]
129 with m
.State("get_a"):
130 with m
.If((self
.in_a_ack
) & (self
.in_a_stb
)):
137 m
.d
.sync
+= self
.in_a_ack
.eq(1)
142 with m
.State("get_b"):
143 with m
.If((self
.in_b_ack
) & (self
.in_b_stb
)):
150 m
.d
.sync
+= self
.in_b_ack
.eq(1)
153 # unpacks operands into sign, mantissa and exponent
155 with m
.State("unpack"):
156 m
.next
= "special_cases"
157 m
.d
.sync
+= a
.decode()
158 m
.d
.sync
+= b
.decode()
161 # special cases: NaNs, infs, zeros, denormalised
163 with m
.State("special_cases"):
165 # if a is NaN or b is NaN return NaN
166 with m
.If(a
.is_nan() | b
.is_nan()):
170 # if a is inf return inf (or NaN)
171 with m
.Elif(a
.is_inf()):
173 m
.d
.sync
+= z
.inf(a
.s
)
174 # if a is inf and signs don't match return NaN
175 with m
.If((b
.e
== 128) & (a
.s
!= b
.s
)):
176 m
.d
.sync
+= z
.nan(b
.s
)
178 # if b is inf return inf
179 with m
.Elif(b
.is_inf()):
181 m
.d
.sync
+= z
.inf(b
.s
)
183 # if a is zero and b zero return signed-a/b
184 with m
.Elif(a
.is_zero() & b
.is_zero()):
186 m
.d
.sync
+= z
.create(a
.s
& b
.s
, b
.e
[0:8], b
.m
[3:26])
188 # if a is zero return b
189 with m
.Elif(a
.is_zero()):
191 m
.d
.sync
+= z
.create(b
.s
, b
.e
[0:8], b
.m
[3:26])
193 # if b is zero return a
194 with m
.Elif(b
.is_zero()):
196 m
.d
.sync
+= z
.create(a
.s
, a
.e
[0:8], a
.m
[3:26])
198 # Denormalised Number checks
201 # denormalise a check
202 with m
.If(a
.e
== a
.N127
):
203 m
.d
.sync
+= a
.e
.eq(-126) # limit a exponent
205 m
.d
.sync
+= a
.m
[26].eq(1) # set top mantissa bit
206 # denormalise b check
207 with m
.If(b
.e
== a
.N127
):
208 m
.d
.sync
+= b
.e
.eq(-126) # limit b exponent
210 m
.d
.sync
+= b
.m
[26].eq(1) # set top mantissa bit
213 # align. NOTE: this does *not* do single-cycle multi-shifting,
214 # it *STAYS* in the align state until the exponents match
216 with m
.State("align"):
217 # exponent of a greater than b: increment b exp, shift b mant
218 with m
.If(a
.e
> b
.e
):
219 m
.d
.sync
+= b
.shift_down()
220 # exponent of b greater than a: increment a exp, shift a mant
221 with m
.Elif(a
.e
< b
.e
):
222 m
.d
.sync
+= a
.shift_down()
223 # exponents equal: move to next stage.
228 # First stage of add. covers same-sign (add) and subtract
229 # special-casing when mantissas are greater or equal, to
230 # give greatest accuracy.
232 with m
.State("add_0"):
234 m
.d
.sync
+= z
.e
.eq(a
.e
)
235 # same-sign (both negative or both positive) add mantissas
236 with m
.If(a
.s
== b
.s
):
241 # a mantissa greater than b, use a
242 with m
.Elif(a
.m
>= b
.m
):
247 # b mantissa greater than a, use b
255 # Second stage of add: preparation for normalisation.
256 # detects when tot sum is too big (tot[27] is kinda a carry bit)
258 with m
.State("add_1"):
259 m
.next
= "normalise_1"
260 # tot[27] gets set when the sum overflows. shift result down
265 round_bit
.eq(tot
[2]),
266 sticky
.eq(tot
[1] | tot
[0]),
274 round_bit
.eq(tot
[1]),
279 # First stage of normalisation.
280 # NOTE: just like "align", this one keeps going round every clock
281 # until the result's exponent is within acceptable "range"
282 # NOTE: the weirdness of reassigning guard and round is due to
283 # the extra mantissa bits coming from tot[0..2]
285 with m
.State("normalise_1"):
286 with m
.If((z
.m
[23] == 0) & (z
.e
> z
.N126
)):
288 z
.e
.eq(z
.e
- 1), # DECREASE exponent
289 z
.m
.eq(z
.m
<< 1), # shift mantissa UP
290 z
.m
[0].eq(guard
), # steal guard bit (was tot[2])
291 guard
.eq(round_bit
), # steal round_bit (was tot[1])
294 m
.next
= "normalise_2"
297 # Second stage of normalisation.
298 # NOTE: just like "align", this one keeps going round every clock
299 # until the result's exponent is within acceptable "range"
300 # NOTE: the weirdness of reassigning guard and round is due to
301 # the extra mantissa bits coming from tot[0..2]
303 with m
.State("normalise_2"):
304 with m
.If(z
.e
< z
.N126
):
306 z
.e
.eq(z
.e
+ 1), # INCREASE exponent
307 z
.m
.eq(z
.m
>> 1), # shift mantissa DOWN
310 sticky
.eq(sticky | round_bit
)
318 with m
.State("round"):
319 m
.next
= "corrections"
320 with m
.If(guard
& (round_bit | sticky | z
.m
[0])):
321 m
.d
.sync
+= z
.m
.eq(z
.m
+ 1) # mantissa rounds up
322 with m
.If(z
.m
== 0xffffff): # all 1s
323 m
.d
.sync
+= z
.e
.eq(z
.e
+ 1) # exponent rounds up
328 with m
.State("corrections"):
330 # denormalised, correct exponent to zero
331 with m
.If(z
.is_denormalised()):
332 m
.d
.sync
+= z
.m
.eq(-127)
333 # FIX SIGN BUG: -a + a = +0.
334 with m
.If((z
.e
== -126) & (z
.m
[0:23] == 0)):
335 m
.d
.sync
+= z
.s
.eq(0)
340 with m
.State("pack"):
342 # if overflow occurs, return inf
343 with m
.If(z
.is_overflowed()):
346 m
.d
.sync
+= z
.create(z
.s
, z
.e
, z
.m
)
351 with m
.State("put_z"):
353 self
.out_z_stb
.eq(1),
356 with m
.If(self
.out_z_stb
& self
.out_z_ack
):
357 m
.d
.sync
+= self
.out_z_stb
.eq(0)
363 if __name__
== "__main__":
364 alu
= FPADD(width
=32)
366 alu
.in_a
, alu
.in_a_stb
, alu
.in_a_ack
,
367 alu
.in_b
, alu
.in_b_stb
, alu
.in_b_ack
,
368 alu
.out_z
, alu
.out_z_stb
, alu
.out_z_ack
,
372 # works... but don't use, just do "python fname.py convert -t v"
373 #print (verilog.convert(alu, ports=[
374 # alu.in_a, alu.in_a_stb, alu.in_a_ack,
375 # alu.in_b, alu.in_b_stb, alu.in_b_ack,
376 # alu.out_z, alu.out_z_stb, alu.out_z_ack,