1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Const
6 from nmigen
.cli
import main
, verilog
10 """ Floating-point Number Class, variable-width TODO (currently 32-bit)
12 Contains signals for an incoming copy of the value, decoded into
13 sign / exponent / mantissa.
14 Also contains encoding functions, creation and recognition of
15 zero, NaN and inf (all signed)
17 Four extra bits are included in the mantissa: the top bit
18 (m[-1]) is effectively a carry-overflow. The other three are
19 guard (m[2]), round (m[1]), and sticky (m[0])
21 def __init__(self
, width
, m_width
=None):
24 m_width
= width
- 5 # mantissa extra bits (top,guard,round)
25 self
.v
= Signal(width
) # Latched copy of value
26 self
.m
= Signal(m_width
) # Mantissa
27 self
.e
= Signal((10, True)) # Exponent: 10 bits, signed
28 self
.s
= Signal() # Sign bit
30 self
.mzero
= Const(0, (m_width
, False))
31 self
.m1s
= Const(-1, (m_width
, False))
32 self
.P128
= Const(128, (10, True))
33 self
.P127
= Const(127, (10, True))
34 self
.N127
= Const(-127, (10, True))
35 self
.N126
= Const(-126, (10, True))
38 """ decodes a latched value into sign / exponent / mantissa
40 bias is subtracted here, from the exponent. exponent
41 is extended to 10 bits so that subtract 127 is done on
45 return [self
.m
.eq(Cat(0, 0, 0, v
[0:23])), # mantissa
46 self
.e
.eq(v
[23:31] - self
.P127
), # exp (minus bias)
47 self
.s
.eq(v
[31]), # sign
50 def create(self
, s
, e
, m
):
51 """ creates a value from sign / exponent / mantissa
53 bias is added here, to the exponent
56 self
.v
[31].eq(s
), # sign
57 self
.v
[23:31].eq(e
+ self
.P127
), # exp (add on bias)
58 self
.v
[0:23].eq(m
) # mantissa
62 """ shifts a mantissa down by one. exponent is increased to compensate
64 accuracy is lost as a result in the mantissa however there are 3
65 guard bits (the latter of which is the "sticky" bit)
67 return [self
.e
.eq(self
.e
+ 1),
68 self
.m
.eq(Cat(self
.m
[0] | self
.m
[1], self
.m
[2:], 0))
72 return self
.create(s
, self
.P128
, 1<<22)
75 return self
.create(s
, self
.P128
, 0)
78 return self
.create(s
, self
.N127
, 0)
81 return (self
.e
== self
.P128
) & (self
.m
!= 0)
84 return (self
.e
== self
.P128
) & (self
.m
== 0)
87 return (self
.e
== self
.N127
) & (self
.m
== self
.mzero
)
89 def is_overflowed(self
):
90 return (self
.e
> self
.P127
)
92 def is_denormalised(self
):
93 return (self
.e
== self
.N126
) & (self
.m
[23] == 0)
96 def __init__(self
, width
):
99 self
.v
= Signal(width
)
104 return [self
.v
, self
.stb
, self
.ack
]
109 self
.guard
= Signal() # tot[2]
110 self
.round_bit
= Signal() # tot[1]
111 self
.sticky
= Signal() # tot[0]
115 def __init__(self
, width
):
118 self
.in_a
= FPOp(width
)
119 self
.in_b
= FPOp(width
)
120 self
.out_z
= FPOp(width
)
122 def get_op(self
, m
, op
, v
, next_state
):
123 with m
.If((op
.ack
) & (op
.stb
)):
130 m
.d
.sync
+= op
.ack
.eq(1)
132 def normalise_1(self
, m
, z
, of
, next_state
):
133 with m
.If((z
.m
[-1] == 0) & (z
.e
> z
.N126
)):
135 z
.e
.eq(z
.e
- 1), # DECREASE exponent
136 z
.m
.eq(z
.m
<< 1), # shift mantissa UP
137 z
.m
[0].eq(of
.guard
), # steal guard bit (was tot[2])
138 of
.guard
.eq(of
.round_bit
), # steal round_bit (was tot[1])
139 of
.round_bit
.eq(0), # reset round bit
144 def normalise_2(self
, m
, z
, of
, next_state
):
145 with m
.If(z
.e
< z
.N126
):
147 z
.e
.eq(z
.e
+ 1), # INCREASE exponent
148 z
.m
.eq(z
.m
>> 1), # shift mantissa DOWN
150 of
.round_bit
.eq(of
.guard
),
151 of
.sticky
.eq(of
.sticky | of
.round_bit
)
156 def get_fragment(self
, platform
=None):
160 a
= FPNum(self
.width
)
161 b
= FPNum(self
.width
)
162 z
= FPNum(self
.width
, 24)
164 tot
= Signal(28) # sticky/round/guard bits, 23 result, 1 overflow
173 with m
.State("get_a"):
174 self
.get_op(m
, self
.in_a
, a
.v
, "get_b")
179 with m
.State("get_b"):
180 self
.get_op(m
, self
.in_b
, b
.v
, "unpack")
183 # unpacks operands into sign, mantissa and exponent
185 with m
.State("unpack"):
186 m
.next
= "special_cases"
187 m
.d
.sync
+= a
.decode()
188 m
.d
.sync
+= b
.decode()
191 # special cases: NaNs, infs, zeros, denormalised
193 with m
.State("special_cases"):
195 # if a is NaN or b is NaN return NaN
196 with m
.If(a
.is_nan() | b
.is_nan()):
200 # if a is inf return inf (or NaN)
201 with m
.Elif(a
.is_inf()):
203 m
.d
.sync
+= z
.inf(a
.s
)
204 # if a is inf and signs don't match return NaN
205 with m
.If((b
.e
== b
.P128
) & (a
.s
!= b
.s
)):
206 m
.d
.sync
+= z
.nan(b
.s
)
208 # if b is inf return inf
209 with m
.Elif(b
.is_inf()):
211 m
.d
.sync
+= z
.inf(b
.s
)
213 # if a is zero and b zero return signed-a/b
214 with m
.Elif(a
.is_zero() & b
.is_zero()):
216 m
.d
.sync
+= z
.create(a
.s
& b
.s
, b
.e
[0:8], b
.m
[3:-1])
218 # if a is zero return b
219 with m
.Elif(a
.is_zero()):
221 m
.d
.sync
+= z
.create(b
.s
, b
.e
[0:8], b
.m
[3:-1])
223 # if b is zero return a
224 with m
.Elif(b
.is_zero()):
226 m
.d
.sync
+= z
.create(a
.s
, a
.e
[0:8], a
.m
[3:-1])
228 # Denormalised Number checks
231 # denormalise a check
232 with m
.If(a
.e
== a
.N127
):
233 m
.d
.sync
+= a
.e
.eq(-126) # limit a exponent
235 m
.d
.sync
+= a
.m
[-1].eq(1) # set top mantissa bit
236 # denormalise b check
237 with m
.If(b
.e
== a
.N127
):
238 m
.d
.sync
+= b
.e
.eq(-126) # limit b exponent
240 m
.d
.sync
+= b
.m
[-1].eq(1) # set top mantissa bit
243 # align. NOTE: this does *not* do single-cycle multi-shifting,
244 # it *STAYS* in the align state until the exponents match
246 with m
.State("align"):
247 # exponent of a greater than b: increment b exp, shift b mant
248 with m
.If(a
.e
> b
.e
):
249 m
.d
.sync
+= b
.shift_down()
250 # exponent of b greater than a: increment a exp, shift a mant
251 with m
.Elif(a
.e
< b
.e
):
252 m
.d
.sync
+= a
.shift_down()
253 # exponents equal: move to next stage.
258 # First stage of add. covers same-sign (add) and subtract
259 # special-casing when mantissas are greater or equal, to
260 # give greatest accuracy.
262 with m
.State("add_0"):
264 m
.d
.sync
+= z
.e
.eq(a
.e
)
265 # same-sign (both negative or both positive) add mantissas
266 with m
.If(a
.s
== b
.s
):
271 # a mantissa greater than b, use a
272 with m
.Elif(a
.m
>= b
.m
):
277 # b mantissa greater than a, use b
285 # Second stage of add: preparation for normalisation.
286 # detects when tot sum is too big (tot[27] is kinda a carry bit)
288 with m
.State("add_1"):
289 m
.next
= "normalise_1"
290 # tot[27] gets set when the sum overflows. shift result down
295 of
.round_bit
.eq(tot
[2]),
296 of
.sticky
.eq(tot
[1] | tot
[0]),
304 of
.round_bit
.eq(tot
[1]),
309 # First stage of normalisation.
310 # NOTE: just like "align", this one keeps going round every clock
311 # until the result's exponent is within acceptable "range"
312 # NOTE: the weirdness of reassigning guard and round is due to
313 # the extra mantissa bits coming from tot[0..2]
315 with m
.State("normalise_1"):
316 self
.normalise_1(m
, z
, of
, "normalise_2")
319 # Second stage of normalisation.
320 # NOTE: just like "align", this one keeps going round every clock
321 # until the result's exponent is within acceptable "range"
322 # NOTE: the weirdness of reassigning guard and round is due to
323 # the extra mantissa bits coming from tot[0..2]
325 with m
.State("normalise_2"):
326 self
.normalise_2(m
, z
, of
, "round")
331 with m
.State("round"):
332 m
.next
= "corrections"
333 with m
.If(of
.guard
& (of
.round_bit | of
.sticky | z
.m
[0])):
334 m
.d
.sync
+= z
.m
.eq(z
.m
+ 1) # mantissa rounds up
335 with m
.If(z
.m
== z
.m1s
): # all 1s
336 m
.d
.sync
+= z
.e
.eq(z
.e
+ 1) # exponent rounds up
341 with m
.State("corrections"):
343 # denormalised, correct exponent to zero
344 with m
.If(z
.is_denormalised()):
345 m
.d
.sync
+= z
.m
.eq(-127)
346 # FIX SIGN BUG: -a + a = +0.
347 with m
.If((z
.e
== z
.N126
) & (z
.m
[0:] == 0)):
348 m
.d
.sync
+= z
.s
.eq(0)
353 with m
.State("pack"):
355 # if overflow occurs, return inf
356 with m
.If(z
.is_overflowed()):
359 m
.d
.sync
+= z
.create(z
.s
, z
.e
, z
.m
)
364 with m
.State("put_z"):
366 self
.out_z
.stb
.eq(1),
369 with m
.If(self
.out_z
.stb
& self
.out_z
.ack
):
370 m
.d
.sync
+= self
.out_z
.stb
.eq(0)
376 if __name__
== "__main__":
377 alu
= FPADD(width
=32)
378 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
381 # works... but don't use, just do "python fname.py convert -t v"
382 #print (verilog.convert(alu, ports=[
383 # ports=alu.in_a.ports() + \
384 # alu.in_b.ports() + \