1 """ Example 5: Making use of PyRTL and Introspection. """
3 from nmigen
import Signal
4 from nmigen
.compat
.fhdl
.bitcontainer
import value_bits_sign
6 # The following example shows how pyrtl can be used to make some interesting
7 # hardware structures using python introspection. In particular, this example
8 # makes a N-stage pipeline structure. Any specific pipeline is then a derived
9 # class of SimplePipeline where methods with names starting with "stage" are
10 # stages, and new members with names not starting with "_" are to be registered
13 class SimplePipeline(object):
14 """ Pipeline builder with auto generation of pipeline registers.
17 def __init__(self
, pipe
):
19 self
._pipeline
_register
_map
= {}
20 self
._current
_stage
_num
= 0
24 for method
in dir(self
):
25 if method
.startswith('stage'):
26 stage_list
.append(method
)
27 for stage
in sorted(stage_list
):
28 stage_method
= getattr(self
, stage
)
30 self
._current
_stage
_num
+= 1
32 def __getattr__(self
, name
):
34 return self
._pipeline
_register
_map
[self
._current
_stage
_num
][name
]
37 'error, no pipeline register "%s" defined for stage %d'
38 % (name
, self
._current
_stage
_num
))
40 def __setattr__(self
, name
, value
):
41 if name
.startswith('_'):
42 # do not do anything tricky with variables starting with '_'
43 object.__setattr
__(self
, name
, value
)
45 next_stage
= self
._current
_stage
_num
+ 1
46 pipereg_id
= str(self
._current
_stage
_num
) + 'to' + str(next_stage
)
47 rname
= 'pipereg_' + pipereg_id
+ '_' + name
48 new_pipereg
= Signal(value_bits_sign(value
), name
=rname
,
50 if next_stage
not in self
._pipeline
_register
_map
:
51 self
._pipeline
_register
_map
[next_stage
] = {}
52 self
._pipeline
_register
_map
[next_stage
][name
] = new_pipereg
53 self
._pipe
.sync
+= new_pipereg
.eq(value
)