1 """ Example 5: Making use of PyRTL and Introspection. """
3 from nmigen
import Module
, Signal
4 from nmigen
.cli
import main
, verilog
7 from pipeline
import SimplePipeline
10 class SimplePipelineExample(SimplePipeline
):
11 """ A very simple pipeline to show how registers are inferred. """
13 def __init__(self
, pipe
):
14 SimplePipeline
.__init
__(self
, pipe
)
15 self
._loopback
= Signal(4)
19 self
.n
= ~self
._loopback
31 self
._pipe
.sync
+= self
._loopback
.eq(self
.n
+ 3)
37 self
.p
= SimplePipelineExample(self
.m
.d
)
39 def get_fragment(self
, platform
=None):
42 if __name__
== "__main__":
43 example
= PipeModule()
48 print(verilog
.convert(example
, ports
=[