1 # Copyright (c) 2014 - 2019 The Regents of the University of
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26 from nmigen
import Module
, Signal
, Memory
, Mux
, Elaboratable
27 from nmigen
.tools
import bits_for
28 from nmigen
.cli
import main
29 from nmigen
.lib
.fifo
import FIFOInterface
31 # translated from https://github.com/freechipsproject/chisel3/blob/a4a29e29c3f1eed18f851dcf10bdc845571dfcb6/src/main/scala/chisel3/util/Decoupled.scala#L185 # noqa
34 class Queue(FIFOInterface
, Elaboratable
):
35 def __init__(self
, width
, depth
, fwft
=True, pipe
=False):
36 """ Queue (FIFO) with pipe mode and first-write fall-through capability
38 * width: width of Queue data in/out
39 * depth: queue depth. NOTE: may be set to 0 (this is ok)
40 * fwft : first-write, fall-through mode (Chisel Queue "flow" mode)
41 * pipe : pipe mode. NOTE: this mode can cause unanticipated
42 problems. when read is enabled, so is writeable.
43 therefore if read is enabled, the data ABSOLUTELY MUST
47 * level: available free space (number of unread entries)
49 din = enq_data, writable = enq_ready, we = enq_valid
50 dout = deq_data, re = deq_ready, readable = deq_valid
52 FIFOInterface
.__init
__(self
, width
, depth
, fwft
)
55 self
.level
= Signal(bits_for(depth
))
57 def elaborate(self
, platform
):
60 # set up an SRAM. XXX bug in Memory: cannot create SRAM of depth 1
61 ram
= Memory(self
.width
, self
.depth
if self
.depth
> 1 else 2)
62 m
.submodules
.ram_read
= ram_read
= ram
.read_port(synchronous
=False)
63 m
.submodules
.ram_write
= ram_write
= ram
.write_port()
66 p_ready_o
= self
.writable
70 n_valid_o
= self
.readable
75 ptr_width
= bits_for(self
.depth
- 1) if self
.depth
> 1 else 0
76 enq_ptr
= Signal(ptr_width
) # cyclic pointer to "insert" point (wrport)
77 deq_ptr
= Signal(ptr_width
) # cyclic pointer to "remove" point (rdport)
78 maybe_full
= Signal() # not reset_less (set by sync)
81 do_enq
= Signal(reset_less
=True)
82 do_deq
= Signal(reset_less
=True)
83 ptr_diff
= Signal(ptr_width
)
84 ptr_match
= Signal(reset_less
=True)
85 empty
= Signal(reset_less
=True)
86 full
= Signal(reset_less
=True)
87 enq_max
= Signal(reset_less
=True)
88 deq_max
= Signal(reset_less
=True)
90 m
.d
.comb
+= [ptr_match
.eq(enq_ptr
== deq_ptr
), # read-ptr = write-ptr
91 ptr_diff
.eq(enq_ptr
- deq_ptr
),
92 enq_max
.eq(enq_ptr
== self
.depth
- 1),
93 deq_max
.eq(deq_ptr
== self
.depth
- 1),
94 empty
.eq(ptr_match
& ~maybe_full
),
95 full
.eq(ptr_match
& maybe_full
),
96 do_enq
.eq(p_ready_o
& p_valid_i
), # write conditions ok
97 do_deq
.eq(n_ready_i
& n_valid_o
), # read conditions ok
99 # set readable and writable (NOTE: see pipe mode below)
100 n_valid_o
.eq(~empty
), # cannot read if empty!
101 p_ready_o
.eq(~full
), # cannot write if full!
103 # set up memory and connect to input and output
104 ram_write
.addr
.eq(enq_ptr
),
105 ram_write
.data
.eq(enq_data
),
106 ram_write
.en
.eq(do_enq
),
107 ram_read
.addr
.eq(deq_ptr
),
108 deq_data
.eq(ram_read
.data
) # NOTE: overridden in fwft mode
111 # under write conditions, SRAM write-pointer moves on next clock
113 m
.d
.sync
+= enq_ptr
.eq(Mux(enq_max
, 0, enq_ptr
+1))
115 # under read conditions, SRAM read-pointer moves on next clock
117 m
.d
.sync
+= deq_ptr
.eq(Mux(deq_max
, 0, deq_ptr
+1))
119 # if read-but-not-write or write-but-not-read, maybe_full set
120 with m
.If(do_enq
!= do_deq
):
121 m
.d
.sync
+= maybe_full
.eq(do_enq
)
123 # first-word fall-through: same as "flow" parameter in Chisel3 Queue
124 # basically instead of relying on the Memory characteristics (which
125 # in FPGAs do not have write-through), then when the queue is empty
126 # take the output directly from the input, i.e. *bypass* the SRAM.
127 # this done combinatorially to give the exact same characteristics
128 # as Memory "write-through"... without relying on a changing API
130 with m
.If(p_valid_i
):
131 m
.d
.comb
+= n_valid_o
.eq(1)
133 m
.d
.comb
+= deq_data
.eq(enq_data
)
134 m
.d
.comb
+= do_deq
.eq(0)
135 with m
.If(n_ready_i
):
136 m
.d
.comb
+= do_enq
.eq(0)
138 # pipe mode: if next stage says it's ready (readable), we
139 # *must* declare the input ready (writeable).
141 with m
.If(n_ready_i
):
142 m
.d
.comb
+= p_ready_o
.eq(1)
144 # set the count (available free space), optimise on power-of-two
145 if self
.depth
== 1 << ptr_width
: # is depth a power of 2
146 m
.d
.comb
+= self
.level
.eq(
147 Mux(maybe_full
& ptr_match
, self
.depth
, 0) | ptr_diff
)
149 m
.d
.comb
+= self
.level
.eq(Mux(ptr_match
,
150 Mux(maybe_full
, self
.depth
, 0),
151 Mux(deq_ptr
> enq_ptr
,
152 self
.depth
+ ptr_diff
,
158 if __name__
== "__main__":
159 reg_stage
= Queue(1, 1, pipe
=True)
160 break_ready_chain_stage
= Queue(1, 1, pipe
=True, fwft
=True)
164 def queue_ports(queue
, name_prefix
):
166 for name
in ["level",
170 port
= getattr(queue
, name
)
171 signal
= Signal(port
.shape(), name
=name_prefix
+name
)
172 m
.d
.comb
+= signal
.eq(port
)
173 retval
.append(signal
)
177 port
= getattr(queue
, name
)
178 signal
= Signal(port
.shape(), name
=name_prefix
+name
)
179 m
.d
.comb
+= port
.eq(signal
)
180 retval
.append(signal
)
182 m
.submodules
.reg_stage
= reg_stage
183 ports
+= queue_ports(reg_stage
, "reg_stage_")
184 m
.submodules
.break_ready_chain_stage
= break_ready_chain_stage
185 ports
+= queue_ports(break_ready_chain_stage
, "break_ready_chain_stage_")