1 """ Pipeline and BufferedPipeline implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedPipeline). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedPipeline by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A convenience class that, because UnbufferedPipeline introduces a single
102 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
103 stage that, duh, delays its (unmodified) input by one clock cycle.
108 nmigen implementation of buffered pipeline stage, based on zipcpu:
109 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
111 this module requires quite a bit of thought to understand how it works
112 (and why it is needed in the first place). reading the above is
113 *strongly* recommended.
115 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
116 the STB / ACK signals to raise and lower (on separate clocks) before
117 data may proceeed (thus only allowing one piece of data to proceed
118 on *ALTERNATE* cycles), the signalling here is a true pipeline
119 where data will flow on *every* clock when the conditions are right.
121 input acceptance conditions are when:
122 * incoming previous-stage strobe (p.i_valid) is HIGH
123 * outgoing previous-stage ready (p.o_ready) is LOW
125 output transmission conditions are when:
126 * outgoing next-stage strobe (n.o_valid) is HIGH
127 * outgoing next-stage ready (n.i_ready) is LOW
129 the tricky bit is when the input has valid data and the output is not
130 ready to accept it. if it wasn't for the clock synchronisation, it
131 would be possible to tell the input "hey don't send that data, we're
132 not ready". unfortunately, it's not possible to "change the past":
133 the previous stage *has no choice* but to pass on its data.
135 therefore, the incoming data *must* be accepted - and stored: that
136 is the responsibility / contract that this stage *must* accept.
137 on the same clock, it's possible to tell the input that it must
138 not send any more data. this is the "stall" condition.
140 we now effectively have *two* possible pieces of data to "choose" from:
141 the buffered data, and the incoming data. the decision as to which
142 to process and output is based on whether we are in "stall" or not.
143 i.e. when the next stage is no longer ready, the output comes from
144 the buffer if a stall had previously occurred, otherwise it comes
145 direct from processing the input.
147 this allows us to respect a synchronous "travelling STB" with what
148 dan calls a "buffered handshake".
150 it's quite a complex state machine!
153 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
154 from nmigen
.cli
import verilog
, rtlil
155 from nmigen
.hdl
.ast
import ArrayProxy
156 from nmigen
.hdl
.rec
import Record
, Layout
158 from abc
import ABCMeta
, abstractmethod
159 from collections
.abc
import Sequence
163 """ contains signals that come *from* the previous stage (both in and out)
164 * i_valid: previous stage indicating all incoming data is valid.
165 may be a multi-bit signal, where all bits are required
166 to be asserted to indicate "valid".
167 * o_ready: output to next stage indicating readiness to accept data
168 * i_data : an input - added by the user of this class
171 def __init__(self
, i_width
=1, stage_ctl
=False):
172 self
.stage_ctl
= stage_ctl
173 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
174 self
.o_ready
= Signal(name
="p_o_ready") # prev <<out self
175 self
.i_data
= None # XXX MUST BE ADDED BY USER
177 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
179 def _connect_in(self
, prev
):
180 """ internal helper function to connect stage to an input source.
181 do not use to connect stage-to-stage!
183 return [self
.i_valid
.eq(prev
.i_valid
),
184 prev
.o_ready
.eq(self
.o_ready
),
185 eq(self
.i_data
, prev
.i_data
),
188 def i_valid_logic(self
):
189 vlen
= len(self
.i_valid
)
190 if vlen
> 1: # multi-bit case: valid only when i_valid is all 1s
191 all1s
= Const(-1, (len(self
.i_valid
), False))
192 return self
.i_valid
== all1s
193 # single-bit i_valid case
198 """ contains the signals that go *to* the next stage (both in and out)
199 * o_valid: output indicating to next stage that data is valid
200 * i_ready: input from next stage indicating that it can accept data
201 * o_data : an output - added by the user of this class
203 def __init__(self
, stage_ctl
=False):
204 self
.stage_ctl
= stage_ctl
205 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
206 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
207 self
.o_data
= None # XXX MUST BE ADDED BY USER
209 self
.s_o_valid
= Signal(name
="n_s_o_vld") # self out>> next
211 def connect_to_next(self
, nxt
):
212 """ helper function to connect to the next stage data/valid/ready.
213 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
214 use this when connecting stage-to-stage
216 return [nxt
.i_valid
.eq(self
.o_valid
),
217 self
.i_ready
.eq(nxt
.o_ready
),
218 eq(nxt
.i_data
, self
.o_data
),
221 def _connect_out(self
, nxt
):
222 """ internal helper function to connect stage to an output source.
223 do not use to connect stage-to-stage!
225 return [nxt
.o_valid
.eq(self
.o_valid
),
226 self
.i_ready
.eq(nxt
.i_ready
),
227 eq(nxt
.o_data
, self
.o_data
),
232 """ makes signals equal: a helper routine which identifies if it is being
233 passed a list (or tuple) of objects, or signals, or Records, and calls
234 the objects' eq function.
236 complex objects (classes) can be used: they must follow the
237 convention of having an eq member function, which takes the
238 responsibility of further calling eq and returning a list of
241 Record is a special (unusual, recursive) case, where the input may be
242 specified as a dictionary (which may contain further dictionaries,
243 recursively), where the field names of the dictionary must match
244 the Record's field spec. Alternatively, an object with the same
245 member names as the Record may be assigned: it does not have to
248 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
249 has an eq function, the object being assigned to it (e.g. a python
250 object) might not. despite the *input* having an eq function,
251 that doesn't help us, because it's the *ArrayProxy* that's being
252 assigned to. so.... we cheat. use the ports() function of the
253 python object, enumerate them, find out the list of Signals that way,
257 if isinstance(o
, dict):
258 for (k
, v
) in o
.items():
259 print ("d-eq", v
, i
[k
])
260 res
.append(v
.eq(i
[k
]))
263 if not isinstance(o
, Sequence
):
265 for (ao
, ai
) in zip(o
, i
):
266 #print ("eq", ao, ai)
267 if isinstance(ao
, Record
):
268 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
269 if isinstance(field_shape
, Layout
):
273 if hasattr(val
, field_name
): # check for attribute
274 val
= getattr(val
, field_name
)
276 val
= val
[field_name
] # dictionary-style specification
277 rres
= eq(ao
.fields
[field_name
], val
)
279 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
281 op
= getattr(ao
, p
.name
)
282 #print (op, p, p.name)
284 if not isinstance(rres
, Sequence
):
289 if not isinstance(rres
, Sequence
):
295 class StageCls(metaclass
=ABCMeta
):
296 """ Class-based "Stage" API. requires instantiation (after derivation)
298 see "Stage API" above.. Note: python does *not* require derivation
299 from this class. All that is required is that the pipelines *have*
300 the functions listed in this class. Derivation from this class
301 is therefore merely a "courtesy" to maintainers.
304 def ispec(self
): pass # REQUIRED
306 def ospec(self
): pass # REQUIRED
308 #def setup(self, m, i): pass # OPTIONAL
310 def process(self
, i
): pass # REQUIRED
313 class Stage(metaclass
=ABCMeta
):
314 """ Static "Stage" API. does not require instantiation (after derivation)
316 see "Stage API" above. Note: python does *not* require derivation
317 from this class. All that is required is that the pipelines *have*
318 the functions listed in this class. Derivation from this class
319 is therefore merely a "courtesy" to maintainers.
331 #def setup(m, i): pass
338 class RecordBasedStage(Stage
):
339 """ convenience class which provides a Records-based layout.
340 honestly it's a lot easier just to create a direct Records-based
341 class (see ExampleAddRecordStage)
343 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
344 self
.in_shape
= in_shape
345 self
.out_shape
= out_shape
346 self
.__process
= processfn
347 self
.__setup
= setupfn
348 def ispec(self
): return Record(self
.in_shape
)
349 def ospec(self
): return Record(self
.out_shape
)
350 def process(seif
, i
): return self
.__process
(i
)
351 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
354 class StageChain(StageCls
):
355 """ pass in a list of stages, and they will automatically be
356 chained together via their input and output specs into a
359 the end result basically conforms to the exact same Stage API.
361 * input to this class will be the input of the first stage
362 * output of first stage goes into input of second
363 * output of second goes into input into third (etc. etc.)
364 * the output of this class will be the output of the last stage
366 def __init__(self
, chain
, specallocate
=False):
368 self
.specallocate
= specallocate
371 return self
.chain
[0].ispec()
374 return self
.chain
[-1].ospec()
376 def setup(self
, m
, i
):
377 for (idx
, c
) in enumerate(self
.chain
):
378 if hasattr(c
, "setup"):
379 c
.setup(m
, i
) # stage may have some module stuff
380 if self
.specallocate
:
381 o
= self
.chain
[idx
].ospec() # last assignment survives
382 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
384 o
= c
.process(i
) # store input into "o"
385 if idx
!= len(self
.chain
)-1:
386 if self
.specallocate
:
387 ni
= self
.chain
[idx
+1].ispec() # new input on next loop
388 m
.d
.comb
+= eq(ni
, o
) # assign to next input
392 self
.o
= o
# last loop is the output
394 def process(self
, i
):
395 return self
.o
# conform to Stage API: return last-loop output
399 """ Common functions for Pipeline API
401 def __init__(self
, in_multi
=None, stage_ctl
=False):
402 """ Base class containing ready/valid/data to previous and next stages
404 * p: contains ready/valid to the previous stage
405 * n: contains ready/valid to the next stage
407 Except when calling Controlbase.connect(), user must also:
408 * add i_data member to PrevControl (p) and
409 * add o_data member to NextControl (n)
411 # set up input and output IO ACK (prev/next ready/valid)
412 self
.p
= PrevControl(in_multi
, stage_ctl
)
413 self
.n
= NextControl(stage_ctl
)
415 def connect_to_next(self
, nxt
):
416 """ helper function to connect to the next stage data/valid/ready.
418 return self
.n
.connect_to_next(nxt
.p
)
420 def _connect_in(self
, prev
):
421 """ internal helper function to connect stage to an input source.
422 do not use to connect stage-to-stage!
424 return self
.p
._connect
_in
(prev
.p
)
426 def _connect_out(self
, nxt
):
427 """ internal helper function to connect stage to an output source.
428 do not use to connect stage-to-stage!
430 return self
.n
._connect
_out
(nxt
.n
)
432 def connect(self
, pipechain
):
433 """ connects a chain (list) of Pipeline instances together and
434 links them to this ControlBase instance:
436 in <----> self <---> out
439 [pipe1, pipe2, pipe3, pipe4]
442 out---in out--in out---in
444 Also takes care of allocating i_data/o_data, by looking up
445 the data spec for each end of the pipechain. i.e It is NOT
446 necessary to allocate self.p.i_data or self.n.o_data manually:
447 this is handled AUTOMATICALLY, here.
449 Basically this function is the direct equivalent of StageChain,
450 except that unlike StageChain, the Pipeline logic is followed.
452 Just as StageChain presents an object that conforms to the
453 Stage API from a list of objects that also conform to the
454 Stage API, an object that calls this Pipeline connect function
455 has the exact same pipeline API as the list of pipline objects
458 Thus it becomes possible to build up larger chains recursively.
459 More complex chains (multi-input, multi-output) will have to be
462 eqs
= [] # collated list of assignment statements
464 # connect inter-chain
465 for i
in range(len(pipechain
)-1):
467 pipe2
= pipechain
[i
+1]
468 eqs
+= pipe1
.connect_to_next(pipe2
)
470 # connect front of chain to ourselves
472 self
.p
.i_data
= front
.stage
.ispec()
473 eqs
+= front
._connect
_in
(self
)
475 # connect end of chain to ourselves
477 self
.n
.o_data
= end
.stage
.ospec()
478 eqs
+= end
._connect
_out
(self
)
482 def set_input(self
, i
):
483 """ helper function to set the input data
485 return eq(self
.p
.i_data
, i
)
488 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
489 self
.n
.o_valid
, self
.p
.o_ready
,
491 if hasattr(self
.p
.i_data
, "ports"):
492 res
+= self
.p
.i_data
.ports()
495 if hasattr(self
.n
.o_data
, "ports"):
496 res
+= self
.n
.o_data
.ports()
502 class BufferedPipeline(ControlBase
):
503 """ buffered pipeline stage. data and strobe signals travel in sync.
504 if ever the input is ready and the output is not, processed data
505 is shunted in a temporary register.
507 Argument: stage. see Stage API above
509 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
510 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
511 stage-1 p.i_data >>in stage n.o_data out>> stage+1
517 input data p.i_data is read (only), is processed and goes into an
518 intermediate result store [process()]. this is updated combinatorially.
520 in a non-stall condition, the intermediate result will go into the
521 output (update_output). however if ever there is a stall, it goes
522 into r_data instead [update_buffer()].
524 when the non-stall condition is released, r_data is the first
525 to be transferred to the output [flush_buffer()], and the stall
528 on the next cycle (as long as stall is not raised again) the
529 input may begin to be processed and transferred directly to output.
532 def __init__(self
, stage
):
533 ControlBase
.__init
__(self
)
536 # set up the input and output data
537 self
.p
.i_data
= stage
.ispec() # input type
538 self
.n
.o_data
= stage
.ospec()
540 def elaborate(self
, platform
):
544 result
= self
.stage
.ospec()
545 r_data
= self
.stage
.ospec()
546 if hasattr(self
.stage
, "setup"):
547 self
.stage
.setup(self
.m
, self
.p
.i_data
)
549 # establish some combinatorial temporaries
550 o_n_validn
= Signal(reset_less
=True)
551 i_p_valid_o_p_ready
= Signal(reset_less
=True)
552 p_i_valid
= Signal(reset_less
=True)
553 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_logic()),
554 o_n_validn
.eq(~self
.n
.o_valid
),
555 i_p_valid_o_p_ready
.eq(p_i_valid
& self
.p
.o_ready
),
558 # store result of processing in combinatorial temporary
559 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
561 # if not in stall condition, update the temporary register
562 with self
.m
.If(self
.p
.o_ready
): # not stalled
563 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
565 with self
.m
.If(self
.n
.i_ready
): # next stage is ready
566 with self
.m
.If(self
.p
.o_ready
): # not stalled
567 # nothing in buffer: send (processed) input direct to output
568 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
569 eq(self
.n
.o_data
, result
), # update output
571 with self
.m
.Else(): # p.o_ready is false, and something in buffer
572 # Flush the [already processed] buffer to the output port.
573 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # declare reg empty
574 eq(self
.n
.o_data
, r_data
), # flush buffer
575 self
.p
.o_ready
.eq(1), # clear stall
577 # ignore input, since p.o_ready is also false.
579 # (n.i_ready) is false here: next stage is ready
580 with self
.m
.Elif(o_n_validn
): # next stage being told "ready"
581 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
582 self
.p
.o_ready
.eq(1), # Keep the buffer empty
583 eq(self
.n
.o_data
, result
), # set output data
586 # (n.i_ready) false and (n.o_valid) true:
587 with self
.m
.Elif(i_p_valid_o_p_ready
):
588 # If next stage *is* ready, and not stalled yet, accept input
589 self
.m
.d
.sync
+= self
.p
.o_ready
.eq(~
(p_i_valid
& self
.n
.o_valid
))
594 class UnbufferedPipeline(ControlBase
):
595 """ A simple pipeline stage with single-clock synchronisation
596 and two-way valid/ready synchronised signalling.
598 Note that a stall in one stage will result in the entire pipeline
601 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
602 travel synchronously with the data: the valid/ready signalling
603 combines in a *combinatorial* fashion. Therefore, a long pipeline
604 chain will lengthen propagation delays.
606 Argument: stage. see Stage API, above
608 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
609 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
610 stage-1 p.i_data >>in stage n.o_data out>> stage+1
618 p.i_data : StageInput, shaped according to ispec
620 p.o_data : StageOutput, shaped according to ospec
622 r_data : input_shape according to ispec
623 A temporary (buffered) copy of a prior (valid) input.
624 This is HELD if the output is not ready. It is updated
626 result: output_shape according to ospec
627 The output of the combinatorial logic. it is updated
628 COMBINATORIALLY (no clock dependence).
631 def __init__(self
, stage
):
632 ControlBase
.__init
__(self
)
635 # set up the input and output data
636 self
.p
.i_data
= stage
.ispec() # input type
637 self
.n
.o_data
= stage
.ospec() # output type
639 def elaborate(self
, platform
):
642 data_valid
= Signal() # is data valid or not
643 r_data
= self
.stage
.ispec() # input type
644 if hasattr(self
.stage
, "setup"):
645 self
.stage
.setup(self
.m
, r_data
)
648 p_i_valid
= Signal(reset_less
=True)
649 pv
= Signal(reset_less
=True)
650 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_logic())
651 self
.m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
653 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
654 self
.m
.d
.comb
+= self
.p
.o_ready
.eq(~data_valid | self
.n
.i_ready
)
655 self
.m
.d
.sync
+= data_valid
.eq(p_i_valid | \
656 (~self
.n
.i_ready
& data_valid
))
658 self
.m
.d
.sync
+= eq(r_data
, self
.p
.i_data
)
659 self
.m
.d
.comb
+= eq(self
.n
.o_data
, self
.stage
.process(r_data
))
663 class PassThroughStage(StageCls
):
664 """ a pass-through stage which has its input data spec equal to its output,
665 and "passes through" its data from input to output.
667 def __init__(self
, iospecfn
):
668 self
.iospecfn
= iospecfn
669 def ispec(self
): return self
.iospecfn()
670 def ospec(self
): return self
.iospecfn()
671 def process(self
, i
): return i
674 class RegisterPipeline(UnbufferedPipeline
):
675 """ A pipeline stage that delays by one clock cycle, creating a
676 sync'd latch out of o_data and o_valid as an indirect byproduct
677 of using PassThroughStage
679 def __init__(self
, iospecfn
):
680 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))