1 """ Pipeline and BufferedPipeline implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedPipeline). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedPipeline by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A convenience class that, because UnbufferedPipeline introduces a single
102 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
103 stage that, duh, delays its (unmodified) input by one clock cycle.
108 nmigen implementation of buffered pipeline stage, based on zipcpu:
109 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
111 this module requires quite a bit of thought to understand how it works
112 (and why it is needed in the first place). reading the above is
113 *strongly* recommended.
115 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
116 the STB / ACK signals to raise and lower (on separate clocks) before
117 data may proceeed (thus only allowing one piece of data to proceed
118 on *ALTERNATE* cycles), the signalling here is a true pipeline
119 where data will flow on *every* clock when the conditions are right.
121 input acceptance conditions are when:
122 * incoming previous-stage strobe (p.i_valid) is HIGH
123 * outgoing previous-stage ready (p.o_ready) is LOW
125 output transmission conditions are when:
126 * outgoing next-stage strobe (n.o_valid) is HIGH
127 * outgoing next-stage ready (n.i_ready) is LOW
129 the tricky bit is when the input has valid data and the output is not
130 ready to accept it. if it wasn't for the clock synchronisation, it
131 would be possible to tell the input "hey don't send that data, we're
132 not ready". unfortunately, it's not possible to "change the past":
133 the previous stage *has no choice* but to pass on its data.
135 therefore, the incoming data *must* be accepted - and stored: that
136 is the responsibility / contract that this stage *must* accept.
137 on the same clock, it's possible to tell the input that it must
138 not send any more data. this is the "stall" condition.
140 we now effectively have *two* possible pieces of data to "choose" from:
141 the buffered data, and the incoming data. the decision as to which
142 to process and output is based on whether we are in "stall" or not.
143 i.e. when the next stage is no longer ready, the output comes from
144 the buffer if a stall had previously occurred, otherwise it comes
145 direct from processing the input.
147 this allows us to respect a synchronous "travelling STB" with what
148 dan calls a "buffered handshake".
150 it's quite a complex state machine!
153 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
154 from nmigen
.cli
import verilog
, rtlil
155 from nmigen
.hdl
.ast
import ArrayProxy
156 from nmigen
.hdl
.rec
import Record
, Layout
158 from abc
import ABCMeta
, abstractmethod
159 from collections
.abc
import Sequence
163 """ contains signals that come *from* the previous stage (both in and out)
164 * i_valid: previous stage indicating all incoming data is valid.
165 may be a multi-bit signal, where all bits are required
166 to be asserted to indicate "valid".
167 * o_ready: output to next stage indicating readiness to accept data
168 * i_data : an input - added by the user of this class
171 def __init__(self
, i_width
=1):
172 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
173 self
.o_ready
= Signal(name
="p_o_ready") # prev <<out self
174 self
.i_data
= None # XXX MUST BE ADDED BY USER
176 def _connect_in(self
, prev
):
177 """ internal helper function to connect stage to an input source.
178 do not use to connect stage-to-stage!
180 return [self
.i_valid
.eq(prev
.i_valid
),
181 prev
.o_ready
.eq(self
.o_ready
),
182 eq(self
.i_data
, prev
.i_data
),
185 def i_valid_logic(self
):
186 vlen
= len(self
.i_valid
)
187 if vlen
> 1: # multi-bit case: valid only when i_valid is all 1s
188 all1s
= Const(-1, (len(self
.i_valid
), False))
189 return self
.i_valid
== all1s
190 # single-bit i_valid case
195 """ contains the signals that go *to* the next stage (both in and out)
196 * o_valid: output indicating to next stage that data is valid
197 * i_ready: input from next stage indicating that it can accept data
198 * o_data : an output - added by the user of this class
201 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
202 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
203 self
.o_data
= None # XXX MUST BE ADDED BY USER
205 def connect_to_next(self
, nxt
):
206 """ helper function to connect to the next stage data/valid/ready.
207 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
208 use this when connecting stage-to-stage
210 print ("connect next", self
, nxt
)
211 return [nxt
.i_valid
.eq(self
.o_valid
),
212 self
.i_ready
.eq(nxt
.o_ready
),
213 eq(nxt
.i_data
, self
.o_data
),
216 def _connect_out(self
, nxt
):
217 """ internal helper function to connect stage to an output source.
218 do not use to connect stage-to-stage!
220 return [nxt
.o_valid
.eq(self
.o_valid
),
221 self
.i_ready
.eq(nxt
.i_ready
),
222 eq(nxt
.o_data
, self
.o_data
),
227 """ makes signals equal: a helper routine which identifies if it is being
228 passed a list (or tuple) of objects, or signals, or Records, and calls
229 the objects' eq function.
231 complex objects (classes) can be used: they must follow the
232 convention of having an eq member function, which takes the
233 responsibility of further calling eq and returning a list of
236 Record is a special (unusual, recursive) case, where the input may be
237 specified as a dictionary (which may contain further dictionaries,
238 recursively), where the field names of the dictionary must match
239 the Record's field spec. Alternatively, an object with the same
240 member names as the Record may be assigned: it does not have to
243 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
244 has an eq function, the object being assigned to it (e.g. a python
245 object) might not. despite the *input* having an eq function,
246 that doesn't help us, because it's the *ArrayProxy* that's being
247 assigned to. so.... we cheat. use the ports() function of the
248 python object, enumerate them, find out the list of Signals that way,
251 if not isinstance(o
, Sequence
):
254 for (ao
, ai
) in zip(o
, i
):
256 if isinstance(ao
, Record
):
257 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
258 if isinstance(field_shape
, Layout
):
262 if hasattr(val
, field_name
): # check for attribute
263 val
= getattr(val
, field_name
)
265 val
= val
[field_name
] # dictionary-style specification
266 rres
= eq(ao
.fields
[field_name
], val
)
268 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
270 op
= getattr(ao
, p
.name
)
271 #print (op, p, p.name)
273 if not isinstance(rres
, Sequence
):
278 if not isinstance(rres
, Sequence
):
284 class StageCls(metaclass
=ABCMeta
):
285 """ Class-based "Stage" API. requires instantiation (after derivation)
287 see "Stage API" above.. Note: python does *not* require derivation
288 from this class. All that is required is that the pipelines *have*
289 the functions listed in this class. Derivation from this class
290 is therefore merely a "courtesy" to maintainers.
293 def ispec(self
): pass # REQUIRED
295 def ospec(self
): pass # REQUIRED
297 #def setup(self, m, i): pass # OPTIONAL
299 def process(self
, i
): pass # REQUIRED
302 class Stage(metaclass
=ABCMeta
):
303 """ Static "Stage" API. does not require instantiation (after derivation)
305 see "Stage API" above. Note: python does *not* require derivation
306 from this class. All that is required is that the pipelines *have*
307 the functions listed in this class. Derivation from this class
308 is therefore merely a "courtesy" to maintainers.
320 #def setup(m, i): pass
327 class RecordBasedStage(Stage
):
328 """ convenience class which provides a Records-based layout.
329 honestly it's a lot easier just to create a direct Records-based
330 class (see ExampleAddRecordStage)
332 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
333 self
.in_shape
= in_shape
334 self
.out_shape
= out_shape
335 self
.__process
= processfn
336 self
.__setup
= setupfn
337 def ispec(self
): return Record(self
.in_shape
)
338 def ospec(self
): return Record(self
.out_shape
)
339 def process(seif
, i
): return self
.__process
(i
)
340 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
343 class StageChain(StageCls
):
344 """ pass in a list of stages, and they will automatically be
345 chained together via their input and output specs into a
348 the end result basically conforms to the exact same Stage API.
350 * input to this class will be the input of the first stage
351 * output of first stage goes into input of second
352 * output of second goes into input into third (etc. etc.)
353 * the output of this class will be the output of the last stage
355 def __init__(self
, chain
):
359 return self
.chain
[0].ispec()
362 return self
.chain
[-1].ospec()
364 def setup(self
, m
, i
):
365 for (idx
, c
) in enumerate(self
.chain
):
366 if hasattr(c
, "setup"):
367 c
.setup(m
, i
) # stage may have some module stuff
368 o
= self
.chain
[idx
].ospec() # only the last assignment survives
369 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
370 if idx
!= len(self
.chain
)-1:
371 ni
= self
.chain
[idx
+1].ispec() # becomes new input on next loop
372 m
.d
.comb
+= eq(ni
, o
) # assign output to next input
374 self
.o
= o
# last loop is the output
376 def process(self
, i
):
377 return self
.o
# conform to Stage API: return last-loop output
381 """ Common functions for Pipeline API
383 def __init__(self
, in_multi
=None):
384 """ Base class containing ready/valid/data to previous and next stages
386 * p: contains ready/valid to the previous stage
387 * n: contains ready/valid to the next stage
389 Except when calling Controlbase.connect(), user must also:
390 * add i_data member to PrevControl (p) and
391 * add o_data member to NextControl (n)
394 # set up input and output IO ACK (prev/next ready/valid)
395 self
.p
= PrevControl(in_multi
)
396 self
.n
= NextControl()
398 def connect_to_next(self
, nxt
):
399 """ helper function to connect to the next stage data/valid/ready.
401 print ("ControlBase connect next", self
, nxt
)
402 return self
.n
.connect_to_next(nxt
.p
)
404 def _connect_in(self
, prev
):
405 """ internal helper function to connect stage to an input source.
406 do not use to connect stage-to-stage!
408 return self
.p
._connect
_in
(prev
.p
)
410 def _connect_out(self
, nxt
):
411 """ internal helper function to connect stage to an output source.
412 do not use to connect stage-to-stage!
414 return self
.n
._connect
_out
(nxt
.n
)
416 def connect(self
, m
, pipechain
):
417 """ connects a chain (list) of Pipeline instances together and
418 links them to this ControlBase instance:
420 in <----> self <---> out
423 [pipe1, pipe2, pipe3, pipe4]
426 out---in out--in out---in
428 Also takes care of allocating i_data/o_data, by looking up
429 the data spec for each end of the pipechain. i.e It is NOT
430 necessary to allocate self.p.i_data or self.n.o_data manually:
431 this is handled AUTOMATICALLY, here.
433 Basically this function is the direct equivalent of StageChain,
434 except that unlike StageChain, the Pipeline logic is followed.
436 Just as StageChain presents an object that conforms to the
437 Stage API from a list of objects that also conform to the
438 Stage API, an object that calls this Pipeline connect function
439 has the exact same pipeline API as the list of pipline objects
442 Thus it becomes possible to build up larger chains recursively.
443 More complex chains (multi-input, multi-output) will have to be
446 eqs
= [] # collated list of assignment statements
448 # connect inter-chain
449 for i
in range(len(pipechain
)-1):
451 pipe2
= pipechain
[i
+1]
452 eqs
+= pipe1
.connect_to_next(pipe2
)
454 # connect front of chain to ourselves
456 #self.p.i_data = front.stage.ispec()
457 eqs
+= front
._connect
_in
(self
)
459 # connect end of chain to ourselves
461 #self.n.o_data = end.stage.ospec()
462 eqs
+= end
._connect
_out
(self
)
464 # activate the assignments
467 def set_input(self
, i
):
468 """ helper function to set the input data
470 return eq(self
.p
.i_data
, i
)
473 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
474 self
.n
.o_valid
, self
.p
.o_ready
,
476 if hasattr(self
.p
.i_data
, "ports"):
477 res
+= self
.p
.i_data
.ports()
480 if hasattr(self
.n
.o_data
, "ports"):
481 res
+= self
.n
.o_data
.ports()
487 class BufferedPipeline(ControlBase
):
488 """ buffered pipeline stage. data and strobe signals travel in sync.
489 if ever the input is ready and the output is not, processed data
490 is shunted in a temporary register.
492 Argument: stage. see Stage API above
494 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
495 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
496 stage-1 p.i_data >>in stage n.o_data out>> stage+1
502 input data p.i_data is read (only), is processed and goes into an
503 intermediate result store [process()]. this is updated combinatorially.
505 in a non-stall condition, the intermediate result will go into the
506 output (update_output). however if ever there is a stall, it goes
507 into r_data instead [update_buffer()].
509 when the non-stall condition is released, r_data is the first
510 to be transferred to the output [flush_buffer()], and the stall
513 on the next cycle (as long as stall is not raised again) the
514 input may begin to be processed and transferred directly to output.
517 def __init__(self
, stage
):
518 ControlBase
.__init
__(self
)
521 # set up the input and output data
522 self
.p
.i_data
= stage
.ispec() # input type
523 self
.n
.o_data
= stage
.ospec()
525 def elaborate(self
, platform
):
528 result
= self
.stage
.ospec()
529 r_data
= self
.stage
.ospec()
530 if hasattr(self
.stage
, "setup"):
531 self
.stage
.setup(m
, self
.p
.i_data
)
533 # establish some combinatorial temporaries
534 o_n_validn
= Signal(reset_less
=True)
535 i_p_valid_o_p_ready
= Signal(reset_less
=True)
536 p_i_valid
= Signal(reset_less
=True)
537 m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_logic()),
538 o_n_validn
.eq(~self
.n
.o_valid
),
539 i_p_valid_o_p_ready
.eq(p_i_valid
& self
.p
.o_ready
),
542 # store result of processing in combinatorial temporary
543 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
545 # if not in stall condition, update the temporary register
546 with m
.If(self
.p
.o_ready
): # not stalled
547 m
.d
.sync
+= eq(r_data
, result
) # update buffer
549 with m
.If(self
.n
.i_ready
): # next stage is ready
550 with m
.If(self
.p
.o_ready
): # not stalled
551 # nothing in buffer: send (processed) input direct to output
552 m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
553 eq(self
.n
.o_data
, result
), # update output
555 with m
.Else(): # p.o_ready is false, and something is in buffer.
556 # Flush the [already processed] buffer to the output port.
557 m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # declare reg empty
558 eq(self
.n
.o_data
, r_data
), # flush buffer
559 self
.p
.o_ready
.eq(1), # clear stall condition
561 # ignore input, since p.o_ready is also false.
563 # (n.i_ready) is false here: next stage is ready
564 with m
.Elif(o_n_validn
): # next stage being told "ready"
565 m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
566 self
.p
.o_ready
.eq(1), # Keep the buffer empty
567 eq(self
.n
.o_data
, result
), # set output data
570 # (n.i_ready) false and (n.o_valid) true:
571 with m
.Elif(i_p_valid_o_p_ready
):
572 # If next stage *is* ready, and not stalled yet, accept input
573 m
.d
.sync
+= self
.p
.o_ready
.eq(~
(p_i_valid
& self
.n
.o_valid
))
578 class UnbufferedPipeline(ControlBase
):
579 """ A simple pipeline stage with single-clock synchronisation
580 and two-way valid/ready synchronised signalling.
582 Note that a stall in one stage will result in the entire pipeline
585 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
586 travel synchronously with the data: the valid/ready signalling
587 combines in a *combinatorial* fashion. Therefore, a long pipeline
588 chain will lengthen propagation delays.
590 Argument: stage. see Stage API, above
592 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
593 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
594 stage-1 p.i_data >>in stage n.o_data out>> stage+1
602 p.i_data : StageInput, shaped according to ispec
604 p.o_data : StageOutput, shaped according to ospec
606 r_data : input_shape according to ispec
607 A temporary (buffered) copy of a prior (valid) input.
608 This is HELD if the output is not ready. It is updated
610 result: output_shape according to ospec
611 The output of the combinatorial logic. it is updated
612 COMBINATORIALLY (no clock dependence).
615 def __init__(self
, stage
):
616 ControlBase
.__init
__(self
)
619 # set up the input and output data
620 self
.p
.i_data
= stage
.ispec() # input type
621 self
.n
.o_data
= stage
.ospec() # output type
623 def elaborate(self
, platform
):
626 data_valid
= Signal() # is data valid or not
627 r_data
= self
.stage
.ispec() # input type
628 if hasattr(self
.stage
, "setup"):
629 self
.stage
.setup(m
, r_data
)
631 p_i_valid
= Signal(reset_less
=True)
632 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_logic())
633 m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
634 m
.d
.comb
+= self
.p
.o_ready
.eq(~data_valid | self
.n
.i_ready
)
635 m
.d
.sync
+= data_valid
.eq(p_i_valid | \
636 (~self
.n
.i_ready
& data_valid
))
637 with m
.If(self
.p
.i_valid
& self
.p
.o_ready
):
638 m
.d
.sync
+= eq(r_data
, self
.p
.i_data
)
639 m
.d
.comb
+= eq(self
.n
.o_data
, self
.stage
.process(r_data
))
643 class PassThroughStage(StageCls
):
644 """ a pass-through stage which has its input data spec equal to its output,
645 and "passes through" its data from input to output.
647 def __init__(self
, iospec
):
648 self
.iospecfn
= iospecfn
649 def ispec(self
): return self
.iospecfn()
650 def ospec(self
): return self
.iospecfn()
651 def process(self
, i
): return i
654 class RegisterPipeline(UnbufferedPipeline
):
655 """ A pipeline stage that delays by one clock cycle, creating a
656 sync'd latch out of o_data and o_valid as an indirect byproduct
657 of using PassThroughStage
659 def __init__(self
, iospecfn
):
660 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))