1 """ Pipeline and BufferedPipeline implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedPipeline). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedPipeline by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A convenience class that, because UnbufferedPipeline introduces a single
102 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
103 stage that, duh, delays its (unmodified) input by one clock cycle.
108 nmigen implementation of buffered pipeline stage, based on zipcpu:
109 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
111 this module requires quite a bit of thought to understand how it works
112 (and why it is needed in the first place). reading the above is
113 *strongly* recommended.
115 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
116 the STB / ACK signals to raise and lower (on separate clocks) before
117 data may proceeed (thus only allowing one piece of data to proceed
118 on *ALTERNATE* cycles), the signalling here is a true pipeline
119 where data will flow on *every* clock when the conditions are right.
121 input acceptance conditions are when:
122 * incoming previous-stage strobe (p.i_valid) is HIGH
123 * outgoing previous-stage ready (p.o_ready) is LOW
125 output transmission conditions are when:
126 * outgoing next-stage strobe (n.o_valid) is HIGH
127 * outgoing next-stage ready (n.i_ready) is LOW
129 the tricky bit is when the input has valid data and the output is not
130 ready to accept it. if it wasn't for the clock synchronisation, it
131 would be possible to tell the input "hey don't send that data, we're
132 not ready". unfortunately, it's not possible to "change the past":
133 the previous stage *has no choice* but to pass on its data.
135 therefore, the incoming data *must* be accepted - and stored: that
136 is the responsibility / contract that this stage *must* accept.
137 on the same clock, it's possible to tell the input that it must
138 not send any more data. this is the "stall" condition.
140 we now effectively have *two* possible pieces of data to "choose" from:
141 the buffered data, and the incoming data. the decision as to which
142 to process and output is based on whether we are in "stall" or not.
143 i.e. when the next stage is no longer ready, the output comes from
144 the buffer if a stall had previously occurred, otherwise it comes
145 direct from processing the input.
147 this allows us to respect a synchronous "travelling STB" with what
148 dan calls a "buffered handshake".
150 it's quite a complex state machine!
153 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
154 from nmigen
.cli
import verilog
, rtlil
155 from nmigen
.hdl
.rec
import Record
, Layout
157 from abc
import ABCMeta
, abstractmethod
158 from collections
.abc
import Sequence
162 """ contains signals that come *from* the previous stage (both in and out)
163 * i_valid: previous stage indicating all incoming data is valid.
164 may be a multi-bit signal, where all bits are required
165 to be asserted to indicate "valid".
166 * o_ready: output to next stage indicating readiness to accept data
167 * i_data : an input - added by the user of this class
170 def __init__(self
, i_width
=1):
171 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
172 self
.o_ready
= Signal(name
="p_o_ready") # prev <<out self
173 self
.i_data
= None # XXX MUST BE ADDED BY USER
175 def _connect_in(self
, prev
):
176 """ internal helper function to connect stage to an input source.
177 do not use to connect stage-to-stage!
179 return [self
.i_valid
.eq(prev
.i_valid
),
180 prev
.o_ready
.eq(self
.o_ready
),
181 eq(self
.i_data
, prev
.i_data
),
184 def i_valid_logic(self
):
185 vlen
= len(self
.i_valid
)
186 if vlen
> 1: # multi-bit case: valid only when i_valid is all 1s
187 all1s
= Const(-1, (len(self
.i_valid
), False))
188 return self
.i_valid
== all1s
189 # single-bit i_valid case
194 """ contains the signals that go *to* the next stage (both in and out)
195 * o_valid: output indicating to next stage that data is valid
196 * i_ready: input from next stage indicating that it can accept data
197 * o_data : an output - added by the user of this class
200 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
201 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
202 self
.o_data
= None # XXX MUST BE ADDED BY USER
204 def connect_to_next(self
, nxt
):
205 """ helper function to connect to the next stage data/valid/ready.
206 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
207 use this when connecting stage-to-stage
209 return [nxt
.i_valid
.eq(self
.o_valid
),
210 self
.i_ready
.eq(nxt
.o_ready
),
211 eq(nxt
.i_data
, self
.o_data
),
214 def _connect_out(self
, nxt
):
215 """ internal helper function to connect stage to an output source.
216 do not use to connect stage-to-stage!
218 return [nxt
.o_valid
.eq(self
.o_valid
),
219 self
.i_ready
.eq(nxt
.i_ready
),
220 eq(nxt
.o_data
, self
.o_data
),
225 """ makes signals equal: a helper routine which identifies if it is being
226 passed a list (or tuple) of objects, or signals, or Records, and calls
227 the objects' eq function.
229 complex objects (classes) can be used: they must follow the
230 convention of having an eq member function, which takes the
231 responsibility of further calling eq and returning a list of
234 Record is a special (unusual, recursive) case, where the input may be
235 specified as a dictionary (which may contain further dictionaries,
236 recursively), where the field names of the dictionary must match
237 the Record's field spec. Alternatively, an object with the same
238 member names as the Record may be assigned: it does not have to
241 if not isinstance(o
, Sequence
):
244 for (ao
, ai
) in zip(o
, i
):
245 #print ("eq", ao, ai)
246 if isinstance(ao
, Record
):
247 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
248 if isinstance(field_shape
, Layout
):
252 if hasattr(val
, field_name
): # check for attribute
253 val
= getattr(val
, field_name
)
255 val
= val
[field_name
] # dictionary-style specification
256 rres
= eq(ao
.fields
[field_name
], val
)
260 if not isinstance(rres
, Sequence
):
266 class StageCls(metaclass
=ABCMeta
):
267 """ Class-based "Stage" API. requires instantiation (after derivation)
269 see "Stage API" above.. Note: python does *not* require derivation
270 from this class. All that is required is that the pipelines *have*
271 the functions listed in this class. Derivation from this class
272 is therefore merely a "courtesy" to maintainers.
275 def ispec(self
): pass # REQUIRED
277 def ospec(self
): pass # REQUIRED
279 #def setup(self, m, i): pass # OPTIONAL
281 def process(self
, i
): pass # REQUIRED
284 class Stage(metaclass
=ABCMeta
):
285 """ Static "Stage" API. does not require instantiation (after derivation)
287 see "Stage API" above. Note: python does *not* require derivation
288 from this class. All that is required is that the pipelines *have*
289 the functions listed in this class. Derivation from this class
290 is therefore merely a "courtesy" to maintainers.
302 #def setup(m, i): pass
309 class RecordBasedStage(Stage
):
310 """ convenience class which provides a Records-based layout.
312 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
313 self
.in_shape
= in_shape
314 self
.out_shape
= out_shape
315 self
.__process
= processfn
316 self
.__setup
= setupfn
317 def ispec(self
): return Record(self
.in_shape
)
318 def ospec(self
): return Record(self
.out_shape
)
319 def process(seif
, i
): return self
.__process
(i
)
320 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
323 class StageChain(StageCls
):
324 """ pass in a list of stages, and they will automatically be
325 chained together via their input and output specs into a
328 the end result basically conforms to the exact same Stage API.
330 * input to this class will be the input of the first stage
331 * output of first stage goes into input of second
332 * output of second goes into input into third (etc. etc.)
333 * the output of this class will be the output of the last stage
335 def __init__(self
, chain
):
339 return self
.chain
[0].ispec()
342 return self
.chain
[-1].ospec()
344 def setup(self
, m
, i
):
345 for (idx
, c
) in enumerate(self
.chain
):
346 if hasattr(c
, "setup"):
347 c
.setup(m
, i
) # stage may have some module stuff
348 o
= self
.chain
[idx
].ospec() # only the last assignment survives
349 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
350 if idx
!= len(self
.chain
)-1:
351 ni
= self
.chain
[idx
+1].ispec() # becomes new input on next loop
352 m
.d
.comb
+= eq(ni
, o
) # assign output to next input
354 self
.o
= o
# last loop is the output
356 def process(self
, i
):
357 return self
.o
# conform to Stage API: return last-loop output
361 """ Common functions for Pipeline API
363 def __init__(self
, in_multi
=None):
364 """ Base class containing ready/valid/data to previous and next stages
366 * p: contains ready/valid to the previous stage
367 * n: contains ready/valid to the next stage
370 * add i_data member to PrevControl (p) and
371 * add o_data member to NextControl (n)
374 # set up input and output IO ACK (prev/next ready/valid)
375 self
.p
= PrevControl(in_multi
)
376 self
.n
= NextControl()
378 def connect_to_next(self
, nxt
):
379 """ helper function to connect to the next stage data/valid/ready.
381 return self
.n
.connect_to_next(nxt
.p
)
383 def _connect_in(self
, prev
):
384 """ internal helper function to connect stage to an input source.
385 do not use to connect stage-to-stage!
387 return self
.p
._connect
_in
(prev
.p
)
389 def _connect_out(self
, nxt
):
390 """ internal helper function to connect stage to an output source.
391 do not use to connect stage-to-stage!
393 return self
.n
._connect
_out
(nxt
.n
)
395 def connect(self
, m
, pipechain
):
396 """ connects a chain (list) of Pipeline instances together and
397 links them to this ControlBase instance:
399 in <----> self <---> out
402 [pipe1, pipe2, pipe3, pipe4]
405 out---in out--in out---in
407 Also takes care of allocating i_data/o_data, by looking up
408 the data spec for each end of the pipechain. i.e It is NOT
409 necessary to allocate self.p.i_data or self.n.o_data manually:
410 this is handled AUTOMATICALLY, here.
412 Basically this function is the direct equivalent of StageChain,
413 except that unlike StageChain, the Pipeline logic is followed.
415 Just as StageChain presents an object that conforms to the
416 Stage API from a list of objects that also conform to the
417 Stage API, an object that calls this Pipeline connect function
418 has the exact same pipeline API as the list of pipline objects
421 Thus it becomes possible to build up larger chains recursively.
422 More complex chains (multi-input, multi-output) will have to be
425 eqs
= [] # collated list of assignment statements
427 # connect inter-chain
428 for i
in range(len(pipechain
)-1):
430 pipe2
= pipechain
[i
+1]
431 eqs
+= pipe1
.connect_to_next(pipe2
)
433 # connect front of chain to ourselves
435 self
.p
.i_data
= front
.stage
.ispec()
436 eqs
+= front
._connect
_in
(self
)
438 # connect end of chain to ourselves
440 self
.n
.o_data
= end
.stage
.ospec()
441 eqs
+= end
._connect
_out
(self
)
443 # activate the assignments
446 def set_input(self
, i
):
447 """ helper function to set the input data
449 return eq(self
.p
.i_data
, i
)
452 return [self
.p
.i_valid
, self
.n
.i_ready
,
453 self
.n
.o_valid
, self
.p
.o_ready
,
454 self
.p
.i_data
, self
.n
.o_data
# XXX need flattening!
458 class BufferedPipeline(ControlBase
):
459 """ buffered pipeline stage. data and strobe signals travel in sync.
460 if ever the input is ready and the output is not, processed data
461 is shunted in a temporary register.
463 Argument: stage. see Stage API above
465 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
466 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
467 stage-1 p.i_data >>in stage n.o_data out>> stage+1
473 input data p.i_data is read (only), is processed and goes into an
474 intermediate result store [process()]. this is updated combinatorially.
476 in a non-stall condition, the intermediate result will go into the
477 output (update_output). however if ever there is a stall, it goes
478 into r_data instead [update_buffer()].
480 when the non-stall condition is released, r_data is the first
481 to be transferred to the output [flush_buffer()], and the stall
484 on the next cycle (as long as stall is not raised again) the
485 input may begin to be processed and transferred directly to output.
488 def __init__(self
, stage
):
489 ControlBase
.__init
__(self
)
492 # set up the input and output data
493 self
.p
.i_data
= stage
.ispec() # input type
494 self
.n
.o_data
= stage
.ospec()
496 def elaborate(self
, platform
):
499 result
= self
.stage
.ospec()
500 r_data
= self
.stage
.ospec()
501 if hasattr(self
.stage
, "setup"):
502 self
.stage
.setup(m
, self
.p
.i_data
)
504 # establish some combinatorial temporaries
505 o_n_validn
= Signal(reset_less
=True)
506 i_p_valid_o_p_ready
= Signal(reset_less
=True)
507 p_i_valid
= Signal(reset_less
=True)
508 m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_logic()),
509 o_n_validn
.eq(~self
.n
.o_valid
),
510 i_p_valid_o_p_ready
.eq(p_i_valid
& self
.p
.o_ready
),
513 # store result of processing in combinatorial temporary
514 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
516 # if not in stall condition, update the temporary register
517 with m
.If(self
.p
.o_ready
): # not stalled
518 m
.d
.sync
+= eq(r_data
, result
) # update buffer
520 with m
.If(self
.n
.i_ready
): # next stage is ready
521 with m
.If(self
.p
.o_ready
): # not stalled
522 # nothing in buffer: send (processed) input direct to output
523 m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
524 eq(self
.n
.o_data
, result
), # update output
526 with m
.Else(): # p.o_ready is false, and something is in buffer.
527 # Flush the [already processed] buffer to the output port.
528 m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # declare reg empty
529 eq(self
.n
.o_data
, r_data
), # flush buffer
530 self
.p
.o_ready
.eq(1), # clear stall condition
532 # ignore input, since p.o_ready is also false.
534 # (n.i_ready) is false here: next stage is ready
535 with m
.Elif(o_n_validn
): # next stage being told "ready"
536 m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
537 self
.p
.o_ready
.eq(1), # Keep the buffer empty
538 eq(self
.n
.o_data
, result
), # set output data
541 # (n.i_ready) false and (n.o_valid) true:
542 with m
.Elif(i_p_valid_o_p_ready
):
543 # If next stage *is* ready, and not stalled yet, accept input
544 m
.d
.sync
+= self
.p
.o_ready
.eq(~
(p_i_valid
& self
.n
.o_valid
))
549 class UnbufferedPipeline(ControlBase
):
550 """ A simple pipeline stage with single-clock synchronisation
551 and two-way valid/ready synchronised signalling.
553 Note that a stall in one stage will result in the entire pipeline
556 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
557 travel synchronously with the data: the valid/ready signalling
558 combines in a *combinatorial* fashion. Therefore, a long pipeline
559 chain will lengthen propagation delays.
561 Argument: stage. see Stage API, above
563 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
564 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
565 stage-1 p.i_data >>in stage n.o_data out>> stage+1
573 p.i_data : StageInput, shaped according to ispec
575 p.o_data : StageOutput, shaped according to ospec
577 r_data : input_shape according to ispec
578 A temporary (buffered) copy of a prior (valid) input.
579 This is HELD if the output is not ready. It is updated
581 result: output_shape according to ospec
582 The output of the combinatorial logic. it is updated
583 COMBINATORIALLY (no clock dependence).
586 def __init__(self
, stage
):
587 ControlBase
.__init
__(self
)
589 self
._data
_valid
= Signal()
591 # set up the input and output data
592 self
.p
.i_data
= stage
.ispec() # input type
593 self
.n
.o_data
= stage
.ospec() # output type
595 def elaborate(self
, platform
):
598 r_data
= self
.stage
.ispec() # input type
599 result
= self
.stage
.ospec() # output data
600 if hasattr(self
.stage
, "setup"):
601 self
.stage
.setup(m
, r_data
)
603 p_i_valid
= Signal(reset_less
=True)
604 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_logic())
605 m
.d
.comb
+= eq(result
, self
.stage
.process(r_data
))
606 m
.d
.comb
+= self
.n
.o_valid
.eq(self
._data
_valid
)
607 m
.d
.comb
+= self
.p
.o_ready
.eq(~self
._data
_valid | self
.n
.i_ready
)
608 m
.d
.sync
+= self
._data
_valid
.eq(p_i_valid | \
609 (~self
.n
.i_ready
& self
._data
_valid
))
610 with m
.If(self
.p
.i_valid
& self
.p
.o_ready
):
611 m
.d
.sync
+= eq(r_data
, self
.p
.i_data
)
612 m
.d
.comb
+= eq(self
.n
.o_data
, result
)
616 class PassThroughStage(StageCls
):
617 """ a pass-through stage which has its input data spec equal to its output,
618 and "passes through" its data from input to output.
620 def __init__(self
, iospec
):
621 self
.iospecfn
= iospecfn
622 def ispec(self
): return self
.iospecfn()
623 def ospec(self
): return self
.iospecfn()
624 def process(self
, i
): return i
627 class RegisterPipeline(UnbufferedPipeline
):
628 """ A pipeline stage that delays by one clock cycle, creating a
629 sync'd latch out of o_data and o_valid as an indirect byproduct
630 of using PassThroughStage
632 def __init__(self
, iospecfn
):
633 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))