1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedHandshake). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedHandshake by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A Control class that introduces a single clock delay, passing its
102 data through unaltered. Unlike RegisterPipeline (which relies
103 on UnbufferedPipeline and PassThroughStage) it handles ready/valid
109 A convenience class that, because UnbufferedPipeline introduces a single
110 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
111 stage that, duh, delays its (unmodified) input by one clock cycle.
116 nmigen implementation of buffered pipeline stage, based on zipcpu:
117 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
119 this module requires quite a bit of thought to understand how it works
120 (and why it is needed in the first place). reading the above is
121 *strongly* recommended.
123 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
124 the STB / ACK signals to raise and lower (on separate clocks) before
125 data may proceeed (thus only allowing one piece of data to proceed
126 on *ALTERNATE* cycles), the signalling here is a true pipeline
127 where data will flow on *every* clock when the conditions are right.
129 input acceptance conditions are when:
130 * incoming previous-stage strobe (p.i_valid) is HIGH
131 * outgoing previous-stage ready (p.o_ready) is LOW
133 output transmission conditions are when:
134 * outgoing next-stage strobe (n.o_valid) is HIGH
135 * outgoing next-stage ready (n.i_ready) is LOW
137 the tricky bit is when the input has valid data and the output is not
138 ready to accept it. if it wasn't for the clock synchronisation, it
139 would be possible to tell the input "hey don't send that data, we're
140 not ready". unfortunately, it's not possible to "change the past":
141 the previous stage *has no choice* but to pass on its data.
143 therefore, the incoming data *must* be accepted - and stored: that
144 is the responsibility / contract that this stage *must* accept.
145 on the same clock, it's possible to tell the input that it must
146 not send any more data. this is the "stall" condition.
148 we now effectively have *two* possible pieces of data to "choose" from:
149 the buffered data, and the incoming data. the decision as to which
150 to process and output is based on whether we are in "stall" or not.
151 i.e. when the next stage is no longer ready, the output comes from
152 the buffer if a stall had previously occurred, otherwise it comes
153 direct from processing the input.
155 this allows us to respect a synchronous "travelling STB" with what
156 dan calls a "buffered handshake".
158 it's quite a complex state machine!
163 Synchronised pipeline, Based on:
164 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
167 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
168 from nmigen
.cli
import verilog
, rtlil
169 from nmigen
.lib
.fifo
import SyncFIFO
170 from nmigen
.hdl
.ast
import ArrayProxy
171 from nmigen
.hdl
.rec
import Record
, Layout
173 from abc
import ABCMeta
, abstractmethod
174 from collections
.abc
import Sequence
178 """ contains signals that come *from* the previous stage (both in and out)
179 * i_valid: previous stage indicating all incoming data is valid.
180 may be a multi-bit signal, where all bits are required
181 to be asserted to indicate "valid".
182 * o_ready: output to next stage indicating readiness to accept data
183 * i_data : an input - added by the user of this class
186 def __init__(self
, i_width
=1, stage_ctl
=False):
187 self
.stage_ctl
= stage_ctl
188 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
189 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
190 self
.i_data
= None # XXX MUST BE ADDED BY USER
192 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
196 """ public-facing API: indicates (externally) that stage is ready
199 return self
.s_o_ready
# set dynamically by stage
200 return self
._o
_ready
# return this when not under dynamic control
202 def _connect_in(self
, prev
, direct
=False):
203 """ internal helper function to connect stage to an input source.
204 do not use to connect stage-to-stage!
207 i_valid
= prev
.i_valid
209 i_valid
= prev
.i_valid_test
210 return [self
.i_valid
.eq(i_valid
),
211 prev
.o_ready
.eq(self
.o_ready
),
212 eq(self
.i_data
, prev
.i_data
),
216 def i_valid_test(self
):
217 vlen
= len(self
.i_valid
)
219 # multi-bit case: valid only when i_valid is all 1s
220 all1s
= Const(-1, (len(self
.i_valid
), False))
221 i_valid
= (self
.i_valid
== all1s
)
223 # single-bit i_valid case
224 i_valid
= self
.i_valid
226 # when stage indicates not ready, incoming data
227 # must "appear" to be not ready too
229 i_valid
= i_valid
& self
.s_o_ready
235 """ contains the signals that go *to* the next stage (both in and out)
236 * o_valid: output indicating to next stage that data is valid
237 * i_ready: input from next stage indicating that it can accept data
238 * o_data : an output - added by the user of this class
240 def __init__(self
, stage_ctl
=False):
241 self
.stage_ctl
= stage_ctl
242 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
243 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
244 self
.o_data
= None # XXX MUST BE ADDED BY USER
246 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
249 def i_ready_test(self
):
251 return self
.i_ready
& self
.d_valid
254 def connect_to_next(self
, nxt
):
255 """ helper function to connect to the next stage data/valid/ready.
256 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
257 use this when connecting stage-to-stage
259 return [nxt
.i_valid
.eq(self
.o_valid
),
260 self
.i_ready
.eq(nxt
.o_ready
),
261 eq(nxt
.i_data
, self
.o_data
),
264 def _connect_out(self
, nxt
, direct
=False):
265 """ internal helper function to connect stage to an output source.
266 do not use to connect stage-to-stage!
269 i_ready
= nxt
.i_ready
271 i_ready
= nxt
.i_ready_test
272 return [nxt
.o_valid
.eq(self
.o_valid
),
273 self
.i_ready
.eq(i_ready
),
274 eq(nxt
.o_data
, self
.o_data
),
279 """ a helper routine which identifies if it is being passed a list
280 (or tuple) of objects, or signals, or Records, and calls
283 the visiting fn is called when an object is identified.
285 Record is a special (unusual, recursive) case, where the input may be
286 specified as a dictionary (which may contain further dictionaries,
287 recursively), where the field names of the dictionary must match
288 the Record's field spec. Alternatively, an object with the same
289 member names as the Record may be assigned: it does not have to
292 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
293 has an eq function, the object being assigned to it (e.g. a python
294 object) might not. despite the *input* having an eq function,
295 that doesn't help us, because it's the *ArrayProxy* that's being
296 assigned to. so.... we cheat. use the ports() function of the
297 python object, enumerate them, find out the list of Signals that way,
300 def visit(self
, o
, i
, act
):
301 if isinstance(o
, dict):
302 return self
.dict_visit(o
, i
, act
)
305 if not isinstance(o
, Sequence
):
307 for (ao
, ai
) in zip(o
, i
):
308 #print ("visit", fn, ao, ai)
309 if isinstance(ao
, Record
):
310 rres
= self
.record_visit(ao
, ai
, act
)
311 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
312 rres
= self
.arrayproxy_visit(ao
, ai
, act
)
314 rres
= act
.fn(ao
, ai
)
318 def dict_visit(self
, o
, i
, act
):
320 for (k
, v
) in o
.items():
321 print ("d-eq", v
, i
[k
])
322 res
.append(act
.fn(v
, i
[k
]))
325 def record_visit(self
, ao
, ai
, act
):
327 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
328 if isinstance(field_shape
, Layout
):
332 if hasattr(val
, field_name
): # check for attribute
333 val
= getattr(val
, field_name
)
335 val
= val
[field_name
] # dictionary-style specification
336 res
+= self
.visit(ao
.fields
[field_name
], val
, act
)
339 def arrayproxy_visit(self
, ao
, ai
, act
):
342 op
= getattr(ao
, p
.name
)
343 #print (op, p, p.name)
344 res
.append(fn(op
, p
))
355 if not isinstance(rres
, Sequence
):
358 def __call__(self
, o
, i
):
359 return self
.visit(o
, i
, self
)
363 """ makes signals equal: a helper routine which identifies if it is being
364 passed a list (or tuple) of objects, or signals, or Records, and calls
365 the objects' eq function.
370 class StageCls(metaclass
=ABCMeta
):
371 """ Class-based "Stage" API. requires instantiation (after derivation)
373 see "Stage API" above.. Note: python does *not* require derivation
374 from this class. All that is required is that the pipelines *have*
375 the functions listed in this class. Derivation from this class
376 is therefore merely a "courtesy" to maintainers.
379 def ispec(self
): pass # REQUIRED
381 def ospec(self
): pass # REQUIRED
383 #def setup(self, m, i): pass # OPTIONAL
385 def process(self
, i
): pass # REQUIRED
388 class Stage(metaclass
=ABCMeta
):
389 """ Static "Stage" API. does not require instantiation (after derivation)
391 see "Stage API" above. Note: python does *not* require derivation
392 from this class. All that is required is that the pipelines *have*
393 the functions listed in this class. Derivation from this class
394 is therefore merely a "courtesy" to maintainers.
406 #def setup(m, i): pass
413 class RecordBasedStage(Stage
):
414 """ convenience class which provides a Records-based layout.
415 honestly it's a lot easier just to create a direct Records-based
416 class (see ExampleAddRecordStage)
418 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
419 self
.in_shape
= in_shape
420 self
.out_shape
= out_shape
421 self
.__process
= processfn
422 self
.__setup
= setupfn
423 def ispec(self
): return Record(self
.in_shape
)
424 def ospec(self
): return Record(self
.out_shape
)
425 def process(seif
, i
): return self
.__process
(i
)
426 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
429 class StageChain(StageCls
):
430 """ pass in a list of stages, and they will automatically be
431 chained together via their input and output specs into a
434 the end result basically conforms to the exact same Stage API.
436 * input to this class will be the input of the first stage
437 * output of first stage goes into input of second
438 * output of second goes into input into third (etc. etc.)
439 * the output of this class will be the output of the last stage
441 def __init__(self
, chain
, specallocate
=False):
443 self
.specallocate
= specallocate
446 return self
.chain
[0].ispec()
449 return self
.chain
[-1].ospec()
451 def _specallocate_setup(self
, m
, i
):
452 for (idx
, c
) in enumerate(self
.chain
):
453 if hasattr(c
, "setup"):
454 c
.setup(m
, i
) # stage may have some module stuff
455 o
= self
.chain
[idx
].ospec() # last assignment survives
456 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
457 if idx
== len(self
.chain
)-1:
459 i
= self
.chain
[idx
+1].ispec() # new input on next loop
460 m
.d
.comb
+= eq(i
, o
) # assign to next input
461 return o
# last loop is the output
463 def _noallocate_setup(self
, m
, i
):
464 for (idx
, c
) in enumerate(self
.chain
):
465 if hasattr(c
, "setup"):
466 c
.setup(m
, i
) # stage may have some module stuff
467 i
= o
= c
.process(i
) # store input into "o"
468 return o
# last loop is the output
470 def setup(self
, m
, i
):
471 if self
.specallocate
:
472 self
.o
= self
._specallocate
_setup
(m
, i
)
474 self
.o
= self
._noallocate
_setup
(m
, i
)
476 def process(self
, i
):
477 return self
.o
# conform to Stage API: return last-loop output
481 """ Common functions for Pipeline API
483 def __init__(self
, stage
=None, in_multi
=None, stage_ctl
=False):
484 """ Base class containing ready/valid/data to previous and next stages
486 * p: contains ready/valid to the previous stage
487 * n: contains ready/valid to the next stage
489 Except when calling Controlbase.connect(), user must also:
490 * add i_data member to PrevControl (p) and
491 * add o_data member to NextControl (n)
495 # set up input and output IO ACK (prev/next ready/valid)
496 self
.p
= PrevControl(in_multi
, stage_ctl
)
497 self
.n
= NextControl(stage_ctl
)
499 # set up the input and output data
500 if stage
is not None:
501 self
.p
.i_data
= stage
.ispec() # input type
502 self
.n
.o_data
= stage
.ospec()
504 def connect_to_next(self
, nxt
):
505 """ helper function to connect to the next stage data/valid/ready.
507 return self
.n
.connect_to_next(nxt
.p
)
509 def _connect_in(self
, prev
):
510 """ internal helper function to connect stage to an input source.
511 do not use to connect stage-to-stage!
513 return self
.p
._connect
_in
(prev
.p
)
515 def _connect_out(self
, nxt
):
516 """ internal helper function to connect stage to an output source.
517 do not use to connect stage-to-stage!
519 return self
.n
._connect
_out
(nxt
.n
)
521 def connect(self
, pipechain
):
522 """ connects a chain (list) of Pipeline instances together and
523 links them to this ControlBase instance:
525 in <----> self <---> out
528 [pipe1, pipe2, pipe3, pipe4]
531 out---in out--in out---in
533 Also takes care of allocating i_data/o_data, by looking up
534 the data spec for each end of the pipechain. i.e It is NOT
535 necessary to allocate self.p.i_data or self.n.o_data manually:
536 this is handled AUTOMATICALLY, here.
538 Basically this function is the direct equivalent of StageChain,
539 except that unlike StageChain, the Pipeline logic is followed.
541 Just as StageChain presents an object that conforms to the
542 Stage API from a list of objects that also conform to the
543 Stage API, an object that calls this Pipeline connect function
544 has the exact same pipeline API as the list of pipline objects
547 Thus it becomes possible to build up larger chains recursively.
548 More complex chains (multi-input, multi-output) will have to be
551 eqs
= [] # collated list of assignment statements
553 # connect inter-chain
554 for i
in range(len(pipechain
)-1):
556 pipe2
= pipechain
[i
+1]
557 eqs
+= pipe1
.connect_to_next(pipe2
)
559 # connect front of chain to ourselves
561 self
.p
.i_data
= front
.stage
.ispec()
562 eqs
+= front
._connect
_in
(self
)
564 # connect end of chain to ourselves
566 self
.n
.o_data
= end
.stage
.ospec()
567 eqs
+= end
._connect
_out
(self
)
571 def set_input(self
, i
):
572 """ helper function to set the input data
574 return eq(self
.p
.i_data
, i
)
577 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
578 self
.n
.o_valid
, self
.p
.o_ready
,
580 if hasattr(self
.p
.i_data
, "ports"):
581 res
+= self
.p
.i_data
.ports()
584 if hasattr(self
.n
.o_data
, "ports"):
585 res
+= self
.n
.o_data
.ports()
590 def _elaborate(self
, platform
):
591 """ handles case where stage has dynamic ready/valid functions
595 if self
.stage
is not None and hasattr(self
.stage
, "setup"):
596 self
.stage
.setup(m
, self
.p
.i_data
)
598 if not self
.p
.stage_ctl
:
601 # intercept the previous (outgoing) "ready", combine with stage ready
602 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
604 # intercept the next (incoming) "ready" and combine it with data valid
605 sdv
= self
.stage
.d_valid(self
.n
.i_ready
)
606 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& sdv
)
611 class BufferedHandshake(ControlBase
):
612 """ buffered pipeline stage. data and strobe signals travel in sync.
613 if ever the input is ready and the output is not, processed data
614 is shunted in a temporary register.
616 Argument: stage. see Stage API above
618 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
619 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
620 stage-1 p.i_data >>in stage n.o_data out>> stage+1
626 input data p.i_data is read (only), is processed and goes into an
627 intermediate result store [process()]. this is updated combinatorially.
629 in a non-stall condition, the intermediate result will go into the
630 output (update_output). however if ever there is a stall, it goes
631 into r_data instead [update_buffer()].
633 when the non-stall condition is released, r_data is the first
634 to be transferred to the output [flush_buffer()], and the stall
637 on the next cycle (as long as stall is not raised again) the
638 input may begin to be processed and transferred directly to output.
641 def elaborate(self
, platform
):
642 self
.m
= ControlBase
._elaborate
(self
, platform
)
644 result
= self
.stage
.ospec()
645 r_data
= self
.stage
.ospec()
647 # establish some combinatorial temporaries
648 o_n_validn
= Signal(reset_less
=True)
649 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
650 nir_por
= Signal(reset_less
=True)
651 nir_por_n
= Signal(reset_less
=True)
652 p_i_valid
= Signal(reset_less
=True)
653 nir_novn
= Signal(reset_less
=True)
654 nirn_novn
= Signal(reset_less
=True)
655 por_pivn
= Signal(reset_less
=True)
656 npnn
= Signal(reset_less
=True)
657 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
658 o_n_validn
.eq(~self
.n
.o_valid
),
659 n_i_ready
.eq(self
.n
.i_ready_test
),
660 nir_por
.eq(n_i_ready
& self
.p
._o
_ready
),
661 nir_por_n
.eq(n_i_ready
& ~self
.p
._o
_ready
),
662 nir_novn
.eq(n_i_ready | o_n_validn
),
663 nirn_novn
.eq(~n_i_ready
& o_n_validn
),
664 npnn
.eq(nir_por | nirn_novn
),
665 por_pivn
.eq(self
.p
._o
_ready
& ~p_i_valid
)
668 # store result of processing in combinatorial temporary
669 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
671 # if not in stall condition, update the temporary register
672 with self
.m
.If(self
.p
.o_ready
): # not stalled
673 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
675 # data pass-through conditions
676 with self
.m
.If(npnn
):
677 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
), # valid if p_valid
678 eq(self
.n
.o_data
, result
), # update output
680 # buffer flush conditions (NOTE: can override data passthru conditions)
681 with self
.m
.If(nir_por_n
): # not stalled
682 # Flush the [already processed] buffer to the output port.
683 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
684 eq(self
.n
.o_data
, r_data
), # flush buffer
686 # output ready conditions
687 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(nir_novn | por_pivn
)
692 class SimpleHandshake(ControlBase
):
693 """ simple handshake control. data and strobe signals travel in sync.
694 implements the protocol used by Wishbone and AXI4.
696 Argument: stage. see Stage API above
698 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
699 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
700 stage-1 p.i_data >>in stage n.o_data out>> stage+1
705 Inputs Temporary Output
706 ------- ---------- -----
707 P P N N PiV& ~NiV& N P
734 def elaborate(self
, platform
):
735 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
738 result
= self
.stage
.ospec()
740 # establish some combinatorial temporaries
741 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
742 p_i_valid_p_o_ready
= Signal(reset_less
=True)
743 p_i_valid
= Signal(reset_less
=True)
744 m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
745 n_i_ready
.eq(self
.n
.i_ready_test
),
746 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
749 # store result of processing in combinatorial temporary
750 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
752 # previous valid and ready
753 with m
.If(p_i_valid_p_o_ready
):
754 m
.d
.sync
+= [r_busy
.eq(1), # output valid
755 eq(self
.n
.o_data
, result
), # update output
757 # previous invalid or not ready, however next is accepting
758 with m
.Elif(n_i_ready
):
759 m
.d
.sync
+= [eq(self
.n
.o_data
, result
)]
760 # TODO: could still send data here (if there was any)
761 #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
762 m
.d
.sync
+= r_busy
.eq(0) # ...so set output invalid
764 m
.d
.comb
+= self
.n
.o_valid
.eq(r_busy
)
765 # if next is ready, so is previous
766 m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
771 class UnbufferedPipeline(ControlBase
):
772 """ A simple pipeline stage with single-clock synchronisation
773 and two-way valid/ready synchronised signalling.
775 Note that a stall in one stage will result in the entire pipeline
778 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
779 travel synchronously with the data: the valid/ready signalling
780 combines in a *combinatorial* fashion. Therefore, a long pipeline
781 chain will lengthen propagation delays.
783 Argument: stage. see Stage API, above
785 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
786 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
787 stage-1 p.i_data >>in stage n.o_data out>> stage+1
795 p.i_data : StageInput, shaped according to ispec
797 p.o_data : StageOutput, shaped according to ospec
799 r_data : input_shape according to ispec
800 A temporary (buffered) copy of a prior (valid) input.
801 This is HELD if the output is not ready. It is updated
803 result: output_shape according to ospec
804 The output of the combinatorial logic. it is updated
805 COMBINATORIALLY (no clock dependence).
837 Note: PoR is *NOT* involved in the above decision-making.
840 def elaborate(self
, platform
):
841 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
843 data_valid
= Signal() # is data valid or not
844 r_data
= self
.stage
.ospec() # output type
847 p_i_valid
= Signal(reset_less
=True)
848 pv
= Signal(reset_less
=True)
849 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
850 m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
852 m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
853 m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
854 m
.d
.sync
+= data_valid
.eq(p_i_valid | \
855 (~self
.n
.i_ready_test
& data_valid
))
857 m
.d
.sync
+= eq(r_data
, self
.stage
.process(self
.p
.i_data
))
858 m
.d
.comb
+= eq(self
.n
.o_data
, r_data
)
863 class UnbufferedPipeline2(ControlBase
):
864 """ A simple pipeline stage with single-clock synchronisation
865 and two-way valid/ready synchronised signalling.
867 Note that a stall in one stage will result in the entire pipeline
870 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
871 travel synchronously with the data: the valid/ready signalling
872 combines in a *combinatorial* fashion. Therefore, a long pipeline
873 chain will lengthen propagation delays.
875 Argument: stage. see Stage API, above
877 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
878 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
879 stage-1 p.i_data >>in stage n.o_data out>> stage+1
884 p.i_data : StageInput, shaped according to ispec
886 p.o_data : StageOutput, shaped according to ospec
888 buf : output_shape according to ospec
889 A temporary (buffered) copy of a valid output
890 This is HELD if the output is not ready. It is updated
894 def elaborate(self
, platform
):
895 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
897 buf_full
= Signal() # is data valid or not
898 buf
= self
.stage
.ospec() # output type
901 p_i_valid
= Signal(reset_less
=True)
902 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
904 m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
905 m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
906 m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& self
.n
.o_valid
)
908 odata
= Mux(buf_full
, buf
, self
.stage
.process(self
.p
.i_data
))
909 m
.d
.comb
+= eq(self
.n
.o_data
, odata
)
910 m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
915 class PassThroughStage(StageCls
):
916 """ a pass-through stage which has its input data spec equal to its output,
917 and "passes through" its data from input to output.
919 def __init__(self
, iospecfn
):
920 self
.iospecfn
= iospecfn
921 def ispec(self
): return self
.iospecfn()
922 def ospec(self
): return self
.iospecfn()
923 def process(self
, i
): return i
926 class PassThroughHandshake(ControlBase
):
927 """ A control block that delays by one clock cycle.
930 def elaborate(self
, platform
):
931 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
934 p_i_valid
= Signal(reset_less
=True)
935 pvr
= Signal(reset_less
=True)
936 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
937 m
.d
.comb
+= pvr
.eq(p_i_valid
& self
.p
.o_ready
)
939 m
.d
.comb
+= self
.p
.o_ready
.eq(~self
.n
.o_valid | self
.n
.i_ready_test
)
940 m
.d
.sync
+= self
.n
.o_valid
.eq(p_i_valid | ~self
.p
.o_ready
)
942 odata
= Mux(pvr
, self
.stage
.process(self
.p
.i_data
), self
.n
.o_data
)
943 m
.d
.sync
+= eq(self
.n
.o_data
, odata
)
948 class RegisterPipeline(UnbufferedPipeline
):
949 """ A pipeline stage that delays by one clock cycle, creating a
950 sync'd latch out of o_data and o_valid as an indirect byproduct
951 of using PassThroughStage
953 def __init__(self
, iospecfn
):
954 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))
957 class FIFOtest(ControlBase
):
958 """ A test of using a SyncFIFO to see if it will work.
959 Note: the only things it will accept is a Signal of width "width".
962 def __init__(self
, width
, depth
):
967 return Signal(width
, name
="data")
968 stage
= PassThroughStage(iospecfn
)
969 ControlBase
.__init
__(self
, stage
=stage
)
971 def elaborate(self
, platform
):
972 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
974 fifo
= SyncFIFO(self
.fwidth
, self
.fdepth
)
975 m
.submodules
.fifo
= fifo
977 # prev: make the FIFO "look" like a PrevControl...
980 fp
._o
_ready
= fifo
.writable
982 # ... so we can do this!
983 m
.d
.comb
+= fp
._connect
_in
(self
.p
, True)
985 # next: make the FIFO "look" like a NextControl...
987 fn
.o_valid
= fifo
.readable
989 fn
.o_data
= fifo
.dout
990 # ... so we can do this!
991 m
.d
.comb
+= fn
._connect
_out
(self
.n
)
993 # err... that should be all!