1 from random
import randint
2 from random
import seed
3 from operator
import add
5 from nmigen
import Module
, Signal
6 from nmigen
.compat
.sim
import run_simulation
8 from nmigen_add_experiment
import FPADD
10 from unit_test_single
import (get_mantissa
, get_exponent
, get_sign
, is_nan
,
11 is_inf
, is_pos_inf
, is_neg_inf
,
12 match
, get_case
, check_case
, run_test
,
16 yield from check_case(dut
, 0xfe34f995, 0xff5d59ad, 0xff800000)
17 yield from check_case(dut
, 0x82471f51, 0x243985f, 0x801c3790)
18 yield from check_case(dut
, 0, 0, 0)
19 yield from check_case(dut
, 0x40000000, 0xc0000000, 0x00000000)
20 yield from check_case(dut
, 0x3F800000, 0x40000000, 0x40400000)
21 yield from check_case(dut
, 0x40000000, 0x3F800000, 0x40400000)
22 yield from check_case(dut
, 0x447A0000, 0x4488B000, 0x4502D800)
23 yield from check_case(dut
, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
24 yield from check_case(dut
, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
25 yield from check_case(dut
, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
26 yield from check_case(dut
, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
27 yield from check_case(dut
, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
28 yield from check_case(dut
, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
29 yield from check_case(dut
, 0xFFFFFFFF, 0xC63B800A, 0xFFC00000)
30 yield from check_case(dut
, 0x7F800000, 0x00000000, 0x7F800000)
31 yield from check_case(dut
, 0x00000000, 0x7F800000, 0x7F800000)
32 yield from check_case(dut
, 0xFF800000, 0x00000000, 0xFF800000)
33 yield from check_case(dut
, 0x00000000, 0xFF800000, 0xFF800000)
34 yield from check_case(dut
, 0x7F800000, 0x7F800000, 0x7F800000)
35 yield from check_case(dut
, 0xFF800000, 0xFF800000, 0xFF800000)
36 yield from check_case(dut
, 0x7F800000, 0xFF800000, 0xFFC00000)
37 yield from check_case(dut
, 0xFF800000, 0x7F800000, 0x7FC00000)
38 yield from check_case(dut
, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
39 yield from check_case(dut
, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
40 yield from check_case(dut
, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
41 yield from check_case(dut
, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
42 yield from check_case(dut
, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
43 yield from check_case(dut
, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
44 yield from check_case(dut
, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
45 yield from check_case(dut
, 0x42500000, 0x51A7A358, 0x51A7A358)
46 yield from check_case(dut
, 0x51A7A358, 0x42500000, 0x51A7A358)
47 yield from check_case(dut
, 0x4E5693A4, 0x42500000, 0x4E5693A5)
48 yield from check_case(dut
, 0x42500000, 0x4E5693A4, 0x4E5693A5)
49 #yield from check_case(dut, 1, 0, 1)
50 #yield from check_case(dut, 1, 1, 1)
55 stimulus_a
= [0x22cb525a, 0x40000000, 0x83e73d5c, 0xbf9b1e94, 0x34082401, 0x5e8ef81, 0x5c75da81, 0x2b017]
56 stimulus_b
= [0xadd79efa, 0xC0000000, 0x1c800000, 0xc038ed3a, 0xb328cd45, 0x114f3db, 0x2f642a39, 0xff3807ab]
57 yield from run_test(dut
, stimulus_a
, stimulus_b
, add
)
58 count
+= len(stimulus_a
)
59 print (count
, "vectors passed")
62 from itertools
import permutations
63 stimulus_a
= [i
[0] for i
in permutations([0x80000000, 0x00000000, 0x7f800000, 0xff800000, 0x7fc00000, 0xffc00000], 2)]
64 stimulus_b
= [i
[1] for i
in permutations([0x80000000, 0x00000000, 0x7f800000, 0xff800000, 0x7fc00000, 0xffc00000], 2)]
65 yield from run_test(dut
, stimulus_a
, stimulus_b
, add
)
66 count
+= len(stimulus_a
)
67 print (count
, "vectors passed")
69 yield from run_edge_cases(dut
, count
, add
)
71 if __name__
== '__main__':
72 dut
= FPADD(width
=32, single_cycle
=True)
73 run_simulation(dut
, testbench(dut
), vcd_name
="test_add.vcd")