1 from nmigen
import Module
, Signal
2 from nmigen
.compat
.sim
import run_simulation
4 from nmigen_add_experiment
import FPADD
12 def get_fragment(self
, platform
=None):
15 m
.d
.comb
+= self
.x
.eq(self
.a | self
.b
)
19 def check_case(dut
, a
, b
, z
):
20 yield dut
.in_a
.v
.eq(a
)
21 yield dut
.in_a
.stb
.eq(1)
24 a_ack
= (yield dut
.in_a
.ack
)
26 yield dut
.in_b
.v
.eq(b
)
27 yield dut
.in_b
.stb
.eq(1)
28 b_ack
= (yield dut
.in_b
.ack
)
33 out_z_stb
= (yield dut
.out_z
.stb
)
36 yield dut
.in_a
.stb
.eq(0)
37 yield dut
.in_b
.stb
.eq(0)
38 yield dut
.out_z
.ack
.eq(1)
40 yield dut
.out_z
.ack
.eq(0)
45 out_z
= yield dut
.out_z
.v
46 assert out_z
== z
, "Output z 0x%x not equal to expected 0x%x" % (out_z
, z
)
49 yield from check_case(dut
, 0, 0, 0)
50 yield from check_case(dut
, 0x3FF0000000000000, 0x4000000000000000,
52 yield from check_case(dut
, 0x4000000000000000, 0x3FF0000000000000,
54 yield from check_case(dut
, 0x4056C00000000000, 0x4042800000000000,
56 yield from check_case(dut
, 0x4056C00000000000, 0x4042EA3D70A3D70A,
60 yield from check_case(dut
, 0x40000000, 0x3F800000, 0x40400000)
61 yield from check_case(dut
, 0x447A0000, 0x4488B000, 0x4502D800)
62 yield from check_case(dut
, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
63 yield from check_case(dut
, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
64 yield from check_case(dut
, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
65 yield from check_case(dut
, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
66 yield from check_case(dut
, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
67 yield from check_case(dut
, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
68 yield from check_case(dut
, 0xFFFFFFFF, 0xC63B800A, 0xFFC00000)
69 yield from check_case(dut
, 0x7F800000, 0x00000000, 0x7F800000)
70 yield from check_case(dut
, 0x00000000, 0x7F800000, 0x7F800000)
71 yield from check_case(dut
, 0xFF800000, 0x00000000, 0xFF800000)
72 yield from check_case(dut
, 0x00000000, 0xFF800000, 0xFF800000)
73 yield from check_case(dut
, 0x7F800000, 0x7F800000, 0x7F800000)
74 yield from check_case(dut
, 0xFF800000, 0xFF800000, 0xFF800000)
75 yield from check_case(dut
, 0x7F800000, 0xFF800000, 0xFFC00000)
76 yield from check_case(dut
, 0xFF800000, 0x7F800000, 0x7FC00000)
77 yield from check_case(dut
, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
78 yield from check_case(dut
, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
79 yield from check_case(dut
, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
80 yield from check_case(dut
, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
81 yield from check_case(dut
, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
82 yield from check_case(dut
, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
83 yield from check_case(dut
, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
84 #yield from check_case(dut, 1, 0, 1)
85 #yield from check_case(dut, 1, 1, 1)
87 if __name__
== '__main__':
88 dut
= FPADD(width
=64, single_cycle
=True)
89 run_simulation(dut
, testbench(dut
), vcd_name
="test_add64.vcd")