1 from nmigen
import Module
, Signal
2 from nmigen
.compat
.sim
import run_simulation
3 from example_buf_pipe
import BufPipe
5 def check_o_n_stb(dut
, val
):
6 o_n_stb
= yield dut
.o_n_stb
11 #yield dut.i_p_rst.eq(1)
12 yield dut
.i_n_busy
.eq(1)
13 yield dut
.o_p_busy
.eq(1)
16 #yield dut.i_p_rst.eq(0)
17 yield dut
.i_n_busy
.eq(0)
18 yield dut
.stage
.i_data
.eq(5)
19 yield dut
.i_p_stb
.eq(1)
22 yield dut
.stage
.i_data
.eq(7)
23 yield from check_o_n_stb(dut
, 0) # effects of i_p_stb delayed
25 yield from check_o_n_stb(dut
, 1) # ok *now* i_p_stb effect is felt
27 yield dut
.stage
.i_data
.eq(2)
29 yield dut
.i_n_busy
.eq(1) # begin going into "stall" (next stage says busy)
30 yield dut
.stage
.i_data
.eq(9)
32 yield dut
.i_p_stb
.eq(0)
33 yield dut
.stage
.i_data
.eq(12)
35 yield dut
.stage
.i_data
.eq(32)
36 yield dut
.i_n_busy
.eq(0)
38 yield from check_o_n_stb(dut
, 1) # buffer still needs to output
40 yield from check_o_n_stb(dut
, 1) # buffer still needs to output
42 yield from check_o_n_stb(dut
, 0) # buffer outputted, *now* we're done.
47 #yield dut.i_p_rst.eq(1)
48 yield dut
.i_n_busy
.eq(1)
49 #yield dut.o_p_busy.eq(1)
52 #yield dut.i_p_rst.eq(0)
53 yield dut
.i_n_busy
.eq(0)
54 yield dut
.i_data
.eq(5)
55 yield dut
.i_p_stb
.eq(1)
58 yield dut
.i_data
.eq(7)
59 yield from check_o_n_stb(dut
, 0) # effects of i_p_stb delayed 2 clocks
61 yield from check_o_n_stb(dut
, 0) # effects of i_p_stb delayed 2 clocks
63 yield dut
.i_data
.eq(2)
65 yield from check_o_n_stb(dut
, 1) # ok *now* i_p_stb effect is felt
66 yield dut
.i_n_busy
.eq(1) # begin going into "stall" (next stage says busy)
67 yield dut
.i_data
.eq(9)
69 yield dut
.i_p_stb
.eq(0)
70 yield dut
.i_data
.eq(12)
72 yield dut
.i_data
.eq(32)
73 yield dut
.i_n_busy
.eq(0)
75 yield from check_o_n_stb(dut
, 1) # buffer still needs to output
77 yield from check_o_n_stb(dut
, 1) # buffer still needs to output
79 yield from check_o_n_stb(dut
, 1) # buffer still needs to output
81 yield from check_o_n_stb(dut
, 0) # buffer outputted, *now* we're done.
89 connect these: ------|---------------|
91 i_p_stb >>in pipe1 o_n_stb out>> i_p_stb >>in pipe2
92 o_p_busy <<out pipe1 i_n_busy <<in o_p_busy <<out pipe2
93 stage.i_data >>in pipe1 o_data out>> stage.i_data >>in pipe2
96 self
.pipe1
= BufPipe()
97 self
.pipe2
= BufPipe()
100 self
.i_p_stb
= Signal() # >>in - comes in from PREVIOUS stage
101 self
.i_n_busy
= Signal() # in<< - comes in from the NEXT stage
102 self
.i_data
= Signal(32) # >>in - comes in from the PREVIOUS stage
105 self
.o_n_stb
= Signal() # out>> - goes out to the NEXT stage
106 self
.o_p_busy
= Signal() # <<out - goes out to the PREVIOUS stage
107 self
.o_data
= Signal(32) # out>> - goes out to the NEXT stage
109 def elaborate(self
, platform
):
111 m
.submodules
.pipe1
= self
.pipe1
112 m
.submodules
.pipe2
= self
.pipe2
114 # connect inter-pipe input/output stb/busy/data
115 m
.d
.comb
+= self
.pipe2
.i_p_stb
.eq(self
.pipe1
.o_n_stb
)
116 m
.d
.comb
+= self
.pipe1
.i_n_busy
.eq(self
.pipe2
.o_p_busy
)
117 m
.d
.comb
+= self
.pipe2
.stage
.i_data
.eq(self
.pipe1
.stage
.o_data
)
119 # inputs/outputs to the module: pipe1 connections here (LHS)
120 m
.d
.comb
+= self
.pipe1
.i_p_stb
.eq(self
.i_p_stb
)
121 m
.d
.comb
+= self
.o_p_busy
.eq(self
.pipe1
.o_p_busy
)
122 m
.d
.comb
+= self
.pipe1
.stage
.i_data
.eq(self
.i_data
)
124 # now pipe2 connections (RHS)
125 m
.d
.comb
+= self
.o_n_stb
.eq(self
.pipe2
.o_n_stb
)
126 m
.d
.comb
+= self
.pipe2
.i_n_busy
.eq(self
.i_n_busy
)
127 m
.d
.comb
+= self
.o_data
.eq(self
.pipe2
.stage
.o_data
)
131 if __name__
== '__main__':
133 run_simulation(dut
, testbench(dut
), vcd_name
="test_bufpipe.vcd")
136 run_simulation(dut
, testbench2(dut
), vcd_name
="test_bufpipe2.vcd")