1 """ Unit tests for Buffered and Unbuffered pipelines
3 contains useful worked examples of how to use the Pipeline API,
6 * Combinatorial Stage "Chaining"
7 * class-based data stages
8 * nmigen module-based data stages
9 * special nmigen module-based data stage, where the stage *is* the module
10 * Record-based data stages
11 * static-class data stages
12 * multi-stage pipelines (and how to connect them)
13 * how to *use* the pipelines (see Test5) - how to get data in and out
17 from nmigen
import Module
, Signal
, Mux
, Const
18 from nmigen
.hdl
.rec
import Record
19 from nmigen
.compat
.sim
import run_simulation
20 from nmigen
.cli
import verilog
, rtlil
22 from example_buf_pipe
import ExampleBufPipe
, ExampleBufPipeAdd
23 from example_buf_pipe
import ExamplePipeline
, UnbufferedPipeline
24 from example_buf_pipe
import ExampleStageCls
25 from example_buf_pipe
import PrevControl
, NextControl
, BufferedPipeline
26 from example_buf_pipe
import StageChain
, ControlBase
, StageCls
27 from singlepipe
import UnbufferedPipeline2
29 from random
import randint
, seed
34 def check_o_n_valid(dut
, val
):
35 o_n_valid
= yield dut
.n
.o_valid
36 assert o_n_valid
== val
38 def check_o_n_valid2(dut
, val
):
39 o_n_valid
= yield dut
.n
.o_valid
40 assert o_n_valid
== val
44 #yield dut.i_p_rst.eq(1)
45 yield dut
.n
.i_ready
.eq(0)
46 yield dut
.p
.o_ready
.eq(0)
49 #yield dut.i_p_rst.eq(0)
50 yield dut
.n
.i_ready
.eq(1)
51 yield dut
.p
.i_data
.eq(5)
52 yield dut
.p
.i_valid
.eq(1)
55 yield dut
.p
.i_data
.eq(7)
56 yield from check_o_n_valid(dut
, 0) # effects of i_p_valid delayed
58 yield from check_o_n_valid(dut
, 1) # ok *now* i_p_valid effect is felt
60 yield dut
.p
.i_data
.eq(2)
62 yield dut
.n
.i_ready
.eq(0) # begin going into "stall" (next stage says ready)
63 yield dut
.p
.i_data
.eq(9)
65 yield dut
.p
.i_valid
.eq(0)
66 yield dut
.p
.i_data
.eq(12)
68 yield dut
.p
.i_data
.eq(32)
69 yield dut
.n
.i_ready
.eq(1)
71 yield from check_o_n_valid(dut
, 1) # buffer still needs to output
73 yield from check_o_n_valid(dut
, 1) # buffer still needs to output
75 yield from check_o_n_valid(dut
, 0) # buffer outputted, *now* we're done.
80 #yield dut.p.i_rst.eq(1)
81 yield dut
.n
.i_ready
.eq(0)
82 #yield dut.p.o_ready.eq(0)
85 #yield dut.p.i_rst.eq(0)
86 yield dut
.n
.i_ready
.eq(1)
87 yield dut
.p
.i_data
.eq(5)
88 yield dut
.p
.i_valid
.eq(1)
91 yield dut
.p
.i_data
.eq(7)
92 yield from check_o_n_valid2(dut
, 0) # effects of i_p_valid delayed 2 clocks
94 yield from check_o_n_valid2(dut
, 0) # effects of i_p_valid delayed 2 clocks
96 yield dut
.p
.i_data
.eq(2)
98 yield from check_o_n_valid2(dut
, 1) # ok *now* i_p_valid effect is felt
99 yield dut
.n
.i_ready
.eq(0) # begin going into "stall" (next stage says ready)
100 yield dut
.p
.i_data
.eq(9)
102 yield dut
.p
.i_valid
.eq(0)
103 yield dut
.p
.i_data
.eq(12)
105 yield dut
.p
.i_data
.eq(32)
106 yield dut
.n
.i_ready
.eq(1)
108 yield from check_o_n_valid2(dut
, 1) # buffer still needs to output
110 yield from check_o_n_valid2(dut
, 1) # buffer still needs to output
112 yield from check_o_n_valid2(dut
, 1) # buffer still needs to output
114 yield from check_o_n_valid2(dut
, 0) # buffer outputted, *now* we're done.
121 def __init__(self
, dut
, resultfn
):
123 self
.resultfn
= resultfn
125 for i
in range(num_tests
):
126 #data.append(randint(0, 1<<16-1))
127 self
.data
.append(i
+1)
132 while self
.o
!= len(self
.data
):
133 send_range
= randint(0, 3)
134 for j
in range(randint(1,10)):
138 send
= randint(0, send_range
) != 0
139 o_p_ready
= yield self
.dut
.p
.o_ready
143 if send
and self
.i
!= len(self
.data
):
144 yield self
.dut
.p
.i_valid
.eq(1)
145 yield self
.dut
.p
.i_data
.eq(self
.data
[self
.i
])
148 yield self
.dut
.p
.i_valid
.eq(0)
152 while self
.o
!= len(self
.data
):
153 stall_range
= randint(0, 3)
154 for j
in range(randint(1,10)):
155 stall
= randint(0, stall_range
) != 0
156 yield self
.dut
.n
.i_ready
.eq(stall
)
158 o_n_valid
= yield self
.dut
.n
.o_valid
159 i_n_ready
= yield self
.dut
.n
.i_ready_test
160 if not o_n_valid
or not i_n_ready
:
162 o_data
= yield self
.dut
.n
.o_data
163 self
.resultfn(o_data
, self
.data
[self
.o
], self
.i
, self
.o
)
165 if self
.o
== len(self
.data
):
168 def test3_resultfn(o_data
, expected
, i
, o
):
169 assert o_data
== expected
+ 1, \
170 "%d-%d data %x not match %x\n" \
171 % (i
, o
, o_data
, expected
)
173 def data_placeholder():
175 for i
in range(num_tests
):
177 d
.src1
= randint(0, 1<<16-1)
178 d
.src2
= randint(0, 1<<16-1)
184 for i
in range(num_tests
):
185 data
.append({'src1': randint(0, 1<<16-1),
186 'src2': randint(0, 1<<16-1)})
191 def __init__(self
, dut
, resultfn
, data
=None, stage_ctl
=False):
193 self
.resultfn
= resultfn
194 self
.stage_ctl
= stage_ctl
199 for i
in range(num_tests
):
200 self
.data
.append((randint(0, 1<<16-1), randint(0, 1<<16-1)))
205 while self
.o
!= len(self
.data
):
206 send_range
= randint(0, 3)
207 for j
in range(randint(1,10)):
211 send
= randint(0, send_range
) != 0
212 o_p_ready
= yield self
.dut
.p
.o_ready
216 if send
and self
.i
!= len(self
.data
):
217 yield self
.dut
.p
.i_valid
.eq(1)
218 for v
in self
.dut
.set_input(self
.data
[self
.i
]):
222 yield self
.dut
.p
.i_valid
.eq(0)
226 while self
.o
!= len(self
.data
):
227 stall_range
= randint(0, 3)
228 for j
in range(randint(1,10)):
229 ready
= randint(0, stall_range
) != 0
231 yield self
.dut
.n
.i_ready
.eq(ready
)
233 o_n_valid
= yield self
.dut
.n
.o_valid
234 i_n_ready
= yield self
.dut
.n
.i_ready_test
235 if not o_n_valid
or not i_n_ready
:
237 if isinstance(self
.dut
.n
.o_data
, Record
):
239 dod
= self
.dut
.n
.o_data
240 for k
, v
in dod
.fields
.items():
243 o_data
= yield self
.dut
.n
.o_data
244 self
.resultfn(o_data
, self
.data
[self
.o
], self
.i
, self
.o
)
246 if self
.o
== len(self
.data
):
249 def test5_resultfn(o_data
, expected
, i
, o
):
250 res
= expected
[0] + expected
[1]
251 assert o_data
== res
, \
252 "%d-%d data %x not match %s\n" \
253 % (i
, o
, o_data
, repr(expected
))
257 for i
in range(num_tests
):
258 #data.append(randint(0, 1<<16-1))
263 stall
= randint(0, 3) != 0
264 send
= randint(0, 5) != 0
265 yield dut
.n
.i_ready
.eq(stall
)
266 o_p_ready
= yield dut
.p
.o_ready
268 if send
and i
!= len(data
):
269 yield dut
.p
.i_valid
.eq(1)
270 yield dut
.p
.i_data
.eq(data
[i
])
273 yield dut
.p
.i_valid
.eq(0)
275 o_n_valid
= yield dut
.n
.o_valid
276 i_n_ready
= yield dut
.n
.i_ready_test
277 if o_n_valid
and i_n_ready
:
278 o_data
= yield dut
.n
.o_data
279 assert o_data
== data
[o
] + 2, "%d-%d data %x not match %x\n" \
280 % (i
, o
, o_data
, data
[o
])
285 ######################################################################
287 ######################################################################
289 class ExampleBufPipe2(ControlBase
):
290 """ Example of how to do chained pipeline stages.
293 def elaborate(self
, platform
):
296 pipe1
= ExampleBufPipe()
297 pipe2
= ExampleBufPipe()
299 m
.submodules
.pipe1
= pipe1
300 m
.submodules
.pipe2
= pipe2
302 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
307 ######################################################################
309 ######################################################################
311 class ExampleBufPipeChain2(BufferedPipeline
):
312 """ connects two stages together as a *single* combinatorial stage.
315 stage1
= ExampleStageCls()
316 stage2
= ExampleStageCls()
317 combined
= StageChain([stage1
, stage2
])
318 BufferedPipeline
.__init
__(self
, combined
)
323 for i
in range(num_tests
):
324 data
.append(randint(0, 1<<16-2))
328 def test9_resultfn(o_data
, expected
, i
, o
):
330 assert o_data
== res
, \
331 "%d-%d received data %x not match expected %x\n" \
332 % (i
, o
, o_data
, res
)
335 ######################################################################
337 ######################################################################
340 def __init__(self
, width
, signed
):
342 self
.src1
= Signal((width
, signed
), name
="src1")
343 self
.src2
= Signal((width
, signed
), name
="src2")
344 self
.output
= Signal(width
, name
="out")
346 def elaborate(self
, platform
):
347 self
.m
.d
.comb
+= self
.output
.eq(Mux(self
.src1
< self
.src2
, 1, 0))
351 class LTStage(StageCls
):
352 """ module-based stage example
355 self
.slt
= SetLessThan(16, True)
358 return (Signal(16, name
="sig1"), Signal(16, "sig2"))
361 return Signal(16, "out")
363 def setup(self
, m
, i
):
365 m
.submodules
.slt
= self
.slt
366 m
.d
.comb
+= self
.slt
.src1
.eq(i
[0])
367 m
.d
.comb
+= self
.slt
.src2
.eq(i
[1])
368 m
.d
.comb
+= self
.o
.eq(self
.slt
.output
)
370 def process(self
, i
):
374 class LTStageDerived(SetLessThan
, StageCls
):
375 """ special version of a nmigen module where the module is also a stage
377 shows that you don't actually need to combinatorially connect
378 to the outputs, or add the module as a submodule: just return
379 the module output parameter(s) from the Stage.process() function
383 SetLessThan
.__init
__(self
, 16, True)
386 return (Signal(16), Signal(16))
391 def setup(self
, m
, i
):
392 m
.submodules
.slt
= self
393 m
.d
.comb
+= self
.src1
.eq(i
[0])
394 m
.d
.comb
+= self
.src2
.eq(i
[1])
396 def process(self
, i
):
400 class ExampleLTPipeline(UnbufferedPipeline
):
401 """ an example of how to use the unbuffered pipeline.
406 UnbufferedPipeline
.__init
__(self
, stage
)
409 class ExampleLTBufferedPipeDerived(BufferedPipeline
):
410 """ an example of how to use the buffered pipeline.
414 stage
= LTStageDerived()
415 BufferedPipeline
.__init
__(self
, stage
)
418 def test6_resultfn(o_data
, expected
, i
, o
):
419 res
= 1 if expected
[0] < expected
[1] else 0
420 assert o_data
== res
, \
421 "%d-%d data %x not match %s\n" \
422 % (i
, o
, o_data
, repr(expected
))
425 ######################################################################
427 ######################################################################
429 class ExampleAddRecordStage(StageCls
):
430 """ example use of a Record
433 record_spec
= [('src1', 16), ('src2', 16)]
435 """ returns a Record using the specification
437 return Record(self
.record_spec
)
440 return Record(self
.record_spec
)
442 def process(self
, i
):
443 """ process the input data, returning a dictionary with key names
444 that exactly match the Record's attributes.
446 return {'src1': i
.src1
+ 1,
449 ######################################################################
451 ######################################################################
453 class ExampleAddRecordPlaceHolderStage(StageCls
):
454 """ example use of a Record, with a placeholder as the processing result
457 record_spec
= [('src1', 16), ('src2', 16)]
459 """ returns a Record using the specification
461 return Record(self
.record_spec
)
464 return Record(self
.record_spec
)
466 def process(self
, i
):
467 """ process the input data, returning a PlaceHolder class instance
468 with attributes that exactly match those of the Record.
476 class PlaceHolder
: pass
479 class ExampleAddRecordPipe(UnbufferedPipeline
):
480 """ an example of how to use the combinatorial pipeline.
484 stage
= ExampleAddRecordStage()
485 UnbufferedPipeline
.__init
__(self
, stage
)
488 def test7_resultfn(o_data
, expected
, i
, o
):
489 res
= (expected
['src1'] + 1, expected
['src2'] + 1)
490 assert o_data
['src1'] == res
[0] and o_data
['src2'] == res
[1], \
491 "%d-%d data %s not match %s\n" \
492 % (i
, o
, repr(o_data
), repr(expected
))
495 class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline
):
496 """ an example of how to use the combinatorial pipeline.
500 stage
= ExampleAddRecordPlaceHolderStage()
501 UnbufferedPipeline
.__init
__(self
, stage
)
504 def test11_resultfn(o_data
, expected
, i
, o
):
505 res1
= expected
.src1
+ 1
506 res2
= expected
.src2
+ 1
507 assert o_data
['src1'] == res1
and o_data
['src2'] == res2
, \
508 "%d-%d data %s not match %s\n" \
509 % (i
, o
, repr(o_data
), repr(expected
))
512 ######################################################################
514 ######################################################################
517 class Example2OpClass
:
518 """ an example of a class used to store 2 operands.
519 requires an eq function, to conform with the pipeline stage API
523 self
.op1
= Signal(16)
524 self
.op2
= Signal(16)
527 return [self
.op1
.eq(i
.op1
), self
.op2
.eq(i
.op2
)]
530 class ExampleAddClassStage(StageCls
):
531 """ an example of how to use the buffered pipeline, as a class instance
535 """ returns an instance of an Example2OpClass.
537 return Example2OpClass()
540 """ returns an output signal which will happen to contain the sum
545 def process(self
, i
):
546 """ process the input data (sums the values in the tuple) and returns it
551 class ExampleBufPipeAddClass(BufferedPipeline
):
552 """ an example of how to use the buffered pipeline, using a class instance
556 addstage
= ExampleAddClassStage()
557 BufferedPipeline
.__init
__(self
, addstage
)
561 """ the eq function, called by set_input, needs an incoming object
562 that conforms to the Example2OpClass.eq function requirements
563 easiest way to do that is to create a class that has the exact
564 same member layout (self.op1, self.op2) as Example2OpClass
566 def __init__(self
, op1
, op2
):
571 def test8_resultfn(o_data
, expected
, i
, o
):
572 res
= expected
.op1
+ expected
.op2
# these are a TestInputAdd instance
573 assert o_data
== res
, \
574 "%d-%d data %x not match %s\n" \
575 % (i
, o
, o_data
, repr(expected
))
579 for i
in range(num_tests
):
580 data
.append(TestInputAdd(randint(0, 1<<16-1), randint(0, 1<<16-1)))
584 ######################################################################
586 ######################################################################
588 class ExampleStageDelayCls(StageCls
):
589 """ an example of how to use the buffered pipeline, in a static class
593 def __init__(self
, valid_trigger
=2):
594 self
.count
= Signal(2)
595 self
.valid_trigger
= valid_trigger
598 return Signal(16, name
="example_input_signal")
601 return Signal(16, name
="example_output_signal")
605 return (self
.count
== 1)# | (self.count == 3)
610 return self
.count
== self
.valid_trigger
613 def process(self
, i
):
614 """ process the input data and returns it (adds 1)
618 def elaborate(self
, platform
):
620 m
.d
.sync
+= self
.count
.eq(self
.count
+ 1)
624 class ExampleBufDelayedPipe(BufferedPipeline
):
627 stage
= ExampleStageDelayCls()
628 BufferedPipeline
.__init
__(self
, stage
, stage_ctl
=True)
630 def elaborate(self
, platform
):
631 m
= BufferedPipeline
.elaborate(self
, platform
)
632 m
.submodules
.stage
= self
.stage
638 for i
in range(num_tests
):
639 #data.append(1<<((i*2)%15))
640 data
.append(randint(0, 1<<16-2))
641 print (hex(data
[-1]))
645 def test12_resultfn(o_data
, expected
, i
, o
):
647 assert o_data
== res
, \
648 "%d-%d data %x not match %x\n" \
649 % (i
, o
, o_data
, res
)
652 ######################################################################
654 ######################################################################
656 class ExampleUnBufDelayedPipe(UnbufferedPipeline
):
659 stage
= ExampleStageDelayCls()
660 UnbufferedPipeline
.__init
__(self
, stage
, stage_ctl
=True)
662 def elaborate(self
, platform
):
663 m
= UnbufferedPipeline
.elaborate(self
, platform
)
664 m
.submodules
.stage
= self
.stage
667 ######################################################################
669 ######################################################################
671 class ExampleBufPipe3(ControlBase
):
672 """ Example of how to do delayed pipeline, where the stage signals
676 def elaborate(self
, platform
):
677 m
= ControlBase
._elaborate
(self
, platform
)
679 pipe1
= ExampleBufDelayedPipe()
680 pipe2
= ExampleBufPipe()
682 m
.submodules
.pipe1
= pipe1
683 m
.submodules
.pipe2
= pipe2
685 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
689 ######################################################################
691 ######################################################################
693 class ExampleBufModeAdd1Pipe(BufferedPipeline
):
696 stage
= ExampleStageCls()
697 BufferedPipeline
.__init
__(self
, stage
, buffermode
=False)
700 class ExampleBufModeUnBufPipe(ControlBase
):
702 def elaborate(self
, platform
):
703 m
= ControlBase
._elaborate
(self
, platform
)
705 pipe1
= ExampleBufModeAdd1Pipe()
706 pipe2
= ExampleBufAdd1Pipe()
708 m
.submodules
.pipe1
= pipe1
709 m
.submodules
.pipe2
= pipe2
711 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
716 ######################################################################
717 # Test 999 - XXX FAILS
718 # http://bugs.libre-riscv.org/show_bug.cgi?id=57
719 ######################################################################
721 class ExampleBufAdd1Pipe(BufferedPipeline
):
724 stage
= ExampleStageCls()
725 BufferedPipeline
.__init
__(self
, stage
)
728 class ExampleUnBufAdd1Pipe(UnbufferedPipeline
):
731 stage
= ExampleStageCls()
732 UnbufferedPipeline
.__init
__(self
, stage
)
735 class ExampleBufUnBufPipe(ControlBase
):
737 def elaborate(self
, platform
):
738 m
= ControlBase
._elaborate
(self
, platform
)
740 # XXX currently fails: any other permutation works fine.
741 # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
742 # also fails using UnbufferedPipeline as well
743 #pipe1 = ExampleUnBufAdd1Pipe()
744 #pipe2 = ExampleBufAdd1Pipe()
745 pipe1
= ExampleBufAdd1Pipe()
746 pipe2
= ExampleUnBufAdd1Pipe()
748 m
.submodules
.pipe1
= pipe1
749 m
.submodules
.pipe2
= pipe2
751 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
756 ######################################################################
758 ######################################################################
762 if __name__
== '__main__':
764 dut
= ExampleBufPipe()
765 run_simulation(dut
, testbench(dut
), vcd_name
="test_bufpipe.vcd")
768 dut
= ExampleBufPipe2()
769 run_simulation(dut
, testbench2(dut
), vcd_name
="test_bufpipe2.vcd")
770 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
771 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
772 [dut
.p
.i_data
] + [dut
.n
.o_data
]
773 vl
= rtlil
.convert(dut
, ports
=ports
)
774 with
open("test_bufpipe2.il", "w") as f
:
779 dut
= ExampleBufPipe()
780 test
= Test3(dut
, test3_resultfn
)
781 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe3.vcd")
784 dut
= ExamplePipeline()
785 test
= Test3(dut
, test3_resultfn
)
786 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_combpipe3.vcd")
789 dut
= ExampleBufPipe2()
790 run_simulation(dut
, testbench4(dut
), vcd_name
="test_bufpipe4.vcd")
793 dut
= ExampleBufPipeAdd()
794 test
= Test5(dut
, test5_resultfn
, stage_ctl
=True)
795 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe5.vcd")
798 dut
= ExampleLTPipeline()
799 test
= Test5(dut
, test6_resultfn
)
800 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_ltcomb6.vcd")
802 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
803 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
804 list(dut
.p
.i_data
) + [dut
.n
.o_data
]
805 vl
= rtlil
.convert(dut
, ports
=ports
)
806 with
open("test_ltcomb_pipe.il", "w") as f
:
810 dut
= ExampleAddRecordPipe()
812 test
= Test5(dut
, test7_resultfn
, data
=data
)
813 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_addrecord.vcd")
815 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
816 dut
.n
.o_valid
, dut
.p
.o_ready
,
817 dut
.p
.i_data
.src1
, dut
.p
.i_data
.src2
,
818 dut
.n
.o_data
.src1
, dut
.n
.o_data
.src2
]
819 vl
= rtlil
.convert(dut
, ports
=ports
)
820 with
open("test_recordcomb_pipe.il", "w") as f
:
824 dut
= ExampleBufPipeAddClass()
826 test
= Test5(dut
, test8_resultfn
, data
=data
)
827 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe8.vcd")
830 dut
= ExampleBufPipeChain2()
831 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
832 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
833 [dut
.p
.i_data
] + [dut
.n
.o_data
]
834 vl
= rtlil
.convert(dut
, ports
=ports
)
835 with
open("test_bufpipechain2.il", "w") as f
:
839 test
= Test5(dut
, test9_resultfn
, data
=data
)
840 run_simulation(dut
, [test
.send
, test
.rcv
],
841 vcd_name
="test_bufpipechain2.vcd")
844 dut
= ExampleLTBufferedPipeDerived()
845 test
= Test5(dut
, test6_resultfn
)
846 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_ltbufpipe10.vcd")
847 vl
= rtlil
.convert(dut
, ports
=ports
)
848 with
open("test_ltbufpipe10.il", "w") as f
:
852 dut
= ExampleAddRecordPlaceHolderPipe()
853 data
=data_placeholder()
854 test
= Test5(dut
, test11_resultfn
, data
=data
)
855 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_addrecord.vcd")
859 dut
= ExampleBufDelayedPipe()
861 test
= Test5(dut
, test12_resultfn
, data
=data
)
862 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe12.vcd")
863 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
864 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
865 [dut
.p
.i_data
] + [dut
.n
.o_data
]
866 vl
= rtlil
.convert(dut
, ports
=ports
)
867 with
open("test_bufpipe12.il", "w") as f
:
871 dut
= ExampleUnBufDelayedPipe()
873 test
= Test5(dut
, test12_resultfn
, data
=data
)
874 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_unbufpipe13.vcd")
875 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
876 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
877 [dut
.p
.i_data
] + [dut
.n
.o_data
]
878 vl
= rtlil
.convert(dut
, ports
=ports
)
879 with
open("test_unbufpipe13.il", "w") as f
:
883 dut
= ExampleBufPipe3()
885 test
= Test5(dut
, test9_resultfn
, data
=data
)
886 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe14.vcd")
887 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
888 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
889 [dut
.p
.i_data
] + [dut
.n
.o_data
]
890 vl
= rtlil
.convert(dut
, ports
=ports
)
891 with
open("test_bufpipe14.il", "w") as f
:
895 dut
= ExampleBufModeUnBufPipe()
897 test
= Test5(dut
, test9_resultfn
, data
=data
)
898 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufunbuf999.vcd")
899 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
900 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
901 [dut
.p
.i_data
] + [dut
.n
.o_data
]
902 vl
= rtlil
.convert(dut
, ports
=ports
)
903 with
open("test_bufunbuf999.il", "w") as f
:
906 print ("test 999 (expected to fail, which is a bug)")
907 dut
= ExampleBufUnBufPipe()
909 test
= Test5(dut
, test9_resultfn
, data
=data
)
910 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufunbuf999.vcd")
911 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
912 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
913 [dut
.p
.i_data
] + [dut
.n
.o_data
]
914 vl
= rtlil
.convert(dut
, ports
=ports
)
915 with
open("test_bufunbuf999.il", "w") as f
: