1 from nmigen
import Module
, Signal
2 from nmigen
.compat
.sim
import run_simulation
4 from nmigen_div_experiment
import FPDIV
12 def elaborate(self
, platform
=None):
15 m
.d
.comb
+= self
.x
.eq(self
.a | self
.b
)
19 def check_case(dut
, a
, b
, z
):
20 yield dut
.in_a
.v
.eq(a
)
21 yield dut
.in_a
.stb
.eq(1)
24 a_ack
= (yield dut
.in_a
.ack
)
26 yield dut
.in_b
.v
.eq(b
)
27 yield dut
.in_b
.stb
.eq(1)
28 b_ack
= (yield dut
.in_b
.ack
)
33 out_z_stb
= (yield dut
.out_z
.stb
)
36 yield dut
.in_a
.stb
.eq(0)
37 yield dut
.in_b
.stb
.eq(0)
38 yield dut
.out_z
.ack
.eq(1)
40 yield dut
.out_z
.ack
.eq(0)
45 out_z
= yield dut
.out_z
.v
46 assert out_z
== z
, "Output z 0x%x not equal to expected 0x%x" % (out_z
, z
)
49 yield from check_case(dut
, 0x4008000000000000, 0x3FF0000000000000,
51 yield from check_case(dut
, 0x3FF0000000000000, 0x4008000000000000,
55 yield from check_case(dut
, 0x3F800000, 0x40000000, 0x3F000000)
56 yield from check_case(dut
, 0x3F800000, 0x40400000, 0x3EAAAAAB)
57 yield from check_case(dut
, 0x40400000, 0x41F80000, 0x3DC6318C)
58 yield from check_case(dut
, 0x41F9EB4D, 0x429A4C70, 0x3ECF52B2)
59 yield from check_case(dut
, 0x7F7FFFFE, 0x70033181, 0x4EF9C4C8)
60 yield from check_case(dut
, 0x7F7FFFFE, 0x70000001, 0x4EFFFFFC)
61 yield from check_case(dut
, 0x7F7FFCFF, 0x70200201, 0x4ECCC7D5)
62 yield from check_case(dut
, 0x70200201, 0x7F7FFCFF, 0x302003E2)
64 if __name__
== '__main__':
66 run_simulation(dut
, testbench(dut
), vcd_name
="test_div64.vcd")