1 """ key strategic example showing how to do multi-input fan-in into a
2 multi-stage pipeline, then multi-output fanout.
4 the multiplex ID from the fan-in is passed in to the pipeline, preserved,
5 and used as a routing ID on the fanout.
8 from random
import randint
10 from nmigen
import Module
, Signal
, Cat
, Value
11 from nmigen
.compat
.sim
import run_simulation
12 from nmigen
.cli
import verilog
, rtlil
14 from nmigen_add_experiment
import (FPADDMuxInOut
,)
18 def __init__(self
, dut
):
23 for mid
in range(dut
.num_rows
):
26 for i
in range(self
.tlen
):
29 self
.di
[mid
][i
] = (op1
, op2
)
30 self
.do
[mid
].append(op1
+ op2
)
33 for i
in range(self
.tlen
):
34 op1
, op2
= self
.di
[mid
][i
]
36 yield rs
.i_valid
.eq(1)
37 yield rs
.i_data
.a
.eq(op1
)
38 yield rs
.i_data
.b
.eq(op2
)
39 yield rs
.i_data
.mid
.eq(mid
)
41 o_p_ready
= yield rs
.o_ready
44 o_p_ready
= yield rs
.o_ready
46 print ("send", mid
, i
, op1
, op2
, op1
+op2
)
48 yield rs
.i_valid
.eq(0)
49 # wait random period of time before queueing another value
50 for i
in range(randint(0, 3)):
53 yield rs
.i_valid
.eq(0)
56 print ("send ended", mid
)
58 ## wait random period of time before queueing another value
59 #for i in range(randint(0, 3)):
62 #send_range = randint(0, 3)
66 # send = randint(0, send_range) != 0
70 #stall_range = randint(0, 3)
71 #for j in range(randint(1,10)):
72 # stall = randint(0, stall_range) != 0
73 # yield self.dut.n[0].i_ready.eq(stall)
78 o_n_valid
= yield n
.o_valid
79 i_n_ready
= yield n
.i_ready
80 if not o_n_valid
or not i_n_ready
:
83 out_mid
= yield n
.o_data
.mid
84 out_z
= yield n
.o_data
.z
86 print ("recv", out_mid
, out_z
)
90 # see if this output has occurred already, delete it if it has
91 assert mid
== out_mid
, "out_mid %d not correct %d" % (out_mid
, mid
)
92 assert self
.do
[mid
][out_i
] == out_z
# pass-through data
93 del self
.do
[mid
][out_i
]
95 # check if there's any more outputs
96 if len(self
.do
[mid
]) == 0:
98 print ("recv ended", mid
)
102 if __name__
== '__main__':
103 dut
= FPADDMuxInOut(16, 2, 4)
104 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
105 with
open("test_fpadd_pipe.il", "w") as f
:
107 #run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")
109 test
= InputTest(dut
)
110 run_simulation(dut
, [test
.rcv(1), test
.rcv(0),
111 test
.rcv(3), test
.rcv(2),
112 test
.send(0), test
.send(1),
113 test
.send(3), test
.send(2),
115 vcd_name
="test_inoutmux_pipe.vcd")