1 from random
import randint
2 from nmigen
import Module
, Signal
3 from nmigen
.compat
.sim
import run_simulation
4 from nmigen
.cli
import verilog
6 from nmigen_add_experiment
import InputGroup
10 stb
= yield dut
.out_op
.stb
12 ack
= yield dut
.out_op
.ack
16 yield dut
.rs
[1].in_op
[0].eq(5)
17 yield dut
.rs
[1].stb
.eq(0b01) # strobe indicate 1st op ready
18 yield dut
.rs
[1].ack
.eq(1)
22 # check row 1 output (should be inactive)
23 decode
= yield dut
.rs
[1].out_decode
25 op0
= yield dut
.rs
[1].out_op
[0]
26 op1
= yield dut
.rs
[1].out_op
[1]
27 assert op0
== 0 and op1
== 0
29 # output should be inactive
30 out_stb
= yield dut
.out_op
.stb
34 yield dut
.rs
[1].in_op
[1].eq(6)
35 yield dut
.rs
[1].stb
.eq(0b11) # strobe indicate both ops ready
39 # row 0 output should be active
40 decode
= yield dut
.rs
[1].out_decode
42 op0
= yield dut
.rs
[1].out_op
[0]
43 op1
= yield dut
.rs
[1].out_op
[1]
44 assert op0
== 5 and op1
== 6
46 # output should be active, MID should be 0 until "ack" is set
47 out_stb
= yield dut
.out_op
.stb
49 out_mid
= yield dut
.mid
52 yield dut
.out_op
.ack
.eq(1)
58 op0
= yield dut
.out_op
.v
[0]
59 op1
= yield dut
.out_op
.v
[1]
60 assert op0
== 5 and op1
== 6
63 if __name__
== '__main__':
64 dut
= InputGroup(width
=32)
65 vl
= verilog
.convert(dut
, ports
=dut
.ports())
66 with
open("test_inputgroup.v", "w") as f
:
68 run_simulation(dut
, testbench(dut
), vcd_name
="test_inputgroup.vcd")