7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def get_mmap_configs(self
):
81 for cfg
in self
.peripheral
.configs
:
82 res
.append(cfg
.get('mmap', None))
83 # XXX HACK! assume all configs same for each peripheral!
86 def get_mmap_cfg_name(self
, idx
):
87 cfg
= self
.get_mmap_configs()
89 nregs
= self
.num_axi_regs32()
90 if isinstance(nregs
, int) or len(nregs
) == 1:
95 def num_axi_regs32cfg(self
):
96 cfg
= self
.get_mmap_configs()
98 return self
.num_axi_regs32()
104 def num_axi_regs32(self
):
107 def slowifdecl(self
):
110 def get_iname(self
, inum
):
111 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
113 def axibase(self
, name
, ifacenum
, idx
):
115 return "%(name)s%(ifacenum)d%(idx)sBase" % locals()
117 def axiend(self
, name
, ifacenum
, idx
):
119 return "%(name)s%(ifacenum)d%(idx)sEnd" % locals()
121 def _axi_reg_def(self
, idx
, numregs
, start
, name
, ifacenum
):
123 offs
= numregs
* 4 * 16
126 end
= start
+ offs
- 1
127 bname
= self
.axibase(name
, ifacenum
, idx
)
128 bend
= self
.axiend(name
, ifacenum
, idx
)
129 comment
= "%d 32-bit regs" % numregs
130 return (" `define %(bname)s 'h%(start)08X\n"
131 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
134 def axi_reg_def(self
, start
, name
, ifacenum
):
135 offs
= self
.num_axi_regs32cfg()
138 if not isinstance(offs
, list):
143 for (idx
, nregs
) in enumerate(offs
):
144 cfg
= self
.get_mmap_cfg_name(idx
)
145 (txt
, off
) = self
._axi
_reg
_def
(cfg
, nregs
, start
, name
, ifacenum
)
149 return ('\n'.join(res
), offstotal
)
151 def axi_master_name(self
, name
, ifacenum
, typ
=''):
153 return "{0}{1}_master_num".format(name
, ifacenum
)
155 def axi_slave_name(self
, idx
, name
, ifacenum
, typ
=''):
157 return "{0}{1}{3}_{2}slave_num".format(name
, ifacenum
, typ
, idx
)
159 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
160 name
= self
.axi_master_name(name
, ifacenum
, typ
)
161 return ("typedef {0} {1};".format(idx
, name
), 1)
163 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
164 offs
= self
.num_axi_regs32()
167 if not isinstance(offs
, list):
170 for (i
, nregs
) in enumerate(offs
):
171 cfg
= self
.get_mmap_cfg_name(i
)
172 name_
= self
.axi_slave_name(cfg
, name
, ifacenum
, typ
)
173 res
.append("typedef {0} {1};".format(idx
+ i
, name_
))
174 return ('\n'.join(res
), len(offs
))
176 def axi_fastaddr_map(self
, name
, ifacenum
):
177 return self
.axi_addr_map(name
, ifacenum
, 'fast')
179 def _axi_addr_map(self
, idx
, name
, ifacenum
, typ
=""):
180 bname
= self
.axibase(name
, ifacenum
, idx
)
181 bend
= self
.axiend(name
, ifacenum
, idx
)
182 name
= self
.axi_slave_name(idx
, name
, ifacenum
, typ
)
184 if(addr>=`{0} && addr<=`{1})
185 return tuple2(True,fromInteger(valueOf({2})));
187 return template
.format(bname
, bend
, name
)
189 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
190 offs
= self
.num_axi_regs32()
193 if not isinstance(offs
, list):
196 for (idx
, nregs
) in enumerate(offs
):
197 cfg
= self
.get_mmap_cfg_name(idx
)
198 res
.append(self
._axi
_addr
_map
(cfg
, name
, ifacenum
, typ
))
199 return '\n'.join(res
)
201 def _mk_pincon(self
, name
, count
, ptyp
):
202 # TODO: really should be using bsv.interface_decl.Interfaces
203 # pin-naming rules.... logic here is hard-coded to duplicate
204 # it (see Interface.__init__ outen)
206 for p
in self
.peripheral
.pinspecs
:
209 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
210 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
211 ret
.append("//%s %s" % (n
, str(p
)))
213 sname
= self
.get_iname(count
)
214 sname
= "{0}.{1}".format(sname
, pname
)
215 ps
= "slow_peripherals.%s" % sname
217 sname
= self
.peripheral
.iname().format(count
)
218 sname
= "{0}.{1}".format(sname
, pname
)
219 ps
= "pinmux.peripheral_side.%s" % sname
220 if typ
== 'out' or typ
== 'inout':
221 fname
= self
.pinname_out(pname
)
222 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
223 n_
= "{0}{1}".format(n
, count
)
231 cn
= self
._mk
_actual
_connection
('out', name
,
233 pname
, ps_
, n_
, fname
)
237 fname
= self
.pinname_outen(pname
)
239 if isinstance(fname
, str):
240 fname
= "{0}.{1}".format(n_
, fname
)
241 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
242 cn
= self
._mk
_actual
_connection
('outen', name
,
246 if typ
== 'in' or typ
== 'inout':
247 fname
= self
.pinname_in(pname
)
253 n_
= "{0}{1}".format(n
, count
)
254 n_
= '{0}.{1}'.format(n_
, fname
)
255 n_
= self
.ifname_tweak(pname
, 'in', n_
)
256 cn
= self
._mk
_actual
_connection
('in', name
,
258 pname
, ps_
, n_
, fname
)
260 return '\n'.join(ret
)
262 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
266 ret
.append("//%s %s %s %s %s" % (name
, ptyp
, typ
, pname
, stype
))
268 sname
= self
.get_iname(count
)
269 ps
= "slow_peripherals.%s" % sname
271 sname
= self
.peripheral
.iname().format(count
)
272 ps
= "pinmux.peripheral_side.%s" % sname
273 n
= self
.get_iname(count
)
275 n
= "{0}.{1}".format(n
, stype
)
276 ps_
= "{0}.{1}".format(ps
, pname
)
277 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
278 pname
, ps_
, n
, stype
)
279 return '\n'.join(ret
)
281 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
282 pname
, ps
, n
, fname
):
284 ck
= self
.get_clock_reset(name
, count
)
286 if ck
== PBase
.get_clock_reset(self
, name
, count
):
287 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
288 .format(ps
, n
, fname
))
290 n2
= "{0}{1}".format(name
, count
)
291 sync
= '{0}_{1}_sync'.format(n2
, pname
)
292 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
294 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
295 .format(sync
, n
, fname
))
296 elif ctype
== 'outen':
297 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
300 if ck
== PBase
.get_clock_reset(self
, name
, count
):
301 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
304 n2
= "{0}{1}".format(name
, count
)
305 sync
= '{0}_{1}_sync'.format(n2
, pname
)
306 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
308 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
312 def _mk_clk_con(self
, name
, count
, ctype
):
314 ck
= self
.get_clock_reset(name
, count
)
315 if ck
== PBase
.get_clock_reset(self
, name
, count
):
318 spc
= self
.get_clk_spc(ctype
)
321 ck
= self
.get_clk_spc(ctype
)
323 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
325 for p
in self
.peripheral
.pinspecs
:
329 if typ
== 'out' or typ
== 'inout':
330 fname
= self
.pinname_out(pname
)
333 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
334 n_
= "{0}{1}".format(n
, count
)
337 n_
= '{0}_{1}'.format(n_
, pname
)
338 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
339 if typ
== 'in' or typ
== 'inout':
340 fname
= self
.pinname_in(pname
)
343 #fname = self.pinname_in(pname)
344 n_
= "{0}{1}".format(n
, count
)
345 n_
= '{0}_{1}'.format(n_
, pname
)
346 #n_ = self.ifname_tweak(pname, 'in', n_)
347 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
348 return '\n'.join(ret
)
350 def get_clk_spc(self
, ctype
):
352 return "sp_clock, sp_reset"
354 return "core_clock, core_reset"
356 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
357 ck
= self
.get_clock_reset(name
, count
)
358 if ck
== PBase
.get_clock_reset(self
, name
, count
):
361 spc
= self
.get_clk_spc(ctype
)
364 ck
= self
.get_clk_spc(ctype
)
366 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
369 n_
= "{0}{1}".format(name
, count
)
370 n_
= '{0}_{1}'.format(n_
, pname
)
371 if typ
== 'in' or typ
== 'inout':
373 return template
.format(bitspec
, n_
, ck
, spc
)
375 def mk_cellconn(self
, *args
):
378 def mkfast_peripheral(self
, size
=0):
381 def mkslow_peripheral(self
, size
=0):
384 def mksuffix(self
, name
, i
):
387 def __mk_connection(self
, con
, aname
, count
, fabricname
):
388 txt
= "mkConnection ({2}.v_to_slaves\n" + \
389 " [fromInteger(valueOf({1}))],\n" + \
392 print "PBase __mk_connection", self
.name
, aname
395 con
= con
.format(count
, aname
)
396 return txt
.format(con
, aname
, fabricname
)
398 def __mk_master_connection(self
, con
, aname
, count
, fabricname
):
399 txt
= "mkConnection ({0}, {2}.v_from_masters\n" + \
400 " [fromInteger(valueOf({1}))]);\n"
402 print "PBase __mk_master_connection", self
.name
, aname
405 con
= con
.format(count
, aname
)
406 return txt
.format(con
, aname
, fabricname
)
408 def mk_master_connection(self
, count
, fabricname
, typ
, name
=None):
409 if not self
.has_axi_master():
413 print "PBase mk_master_conn", self
.name
, count
414 aname
= self
.axi_master_name(name
, count
, typ
)
416 connections
= self
._mk
_connection
(name
, count
, True)
417 if not isinstance(connections
, list):
418 connections
= [connections
]
419 for con
in connections
:
420 ret
.append(self
.__mk
_master
_connection
(con
, aname
, count
,
422 return '\n'.join(ret
)
424 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
427 print "PBase mk_conn", self
.name
, count
429 connections
= self
._mk
_connection
(name
, count
)
430 if not isinstance(connections
, list):
431 connections
= [connections
]
432 for (idx
, con
) in enumerate(connections
):
433 if len(connections
) == 1:
437 aname
= self
.axi_slave_name(idx
, name
, count
, typ
)
438 ret
.append(self
.__mk
_connection
(con
, aname
, count
, fabricname
))
439 return '\n'.join(ret
)
441 def _mk_connection(self
, name
=None, count
=0):
444 def pinname_out(self
, pname
):
447 def pinname_in(self
, pname
):
450 def pinname_outen(self
, pname
):
453 def ifname_tweak(self
, pname
, typ
, txt
):
456 def pinname_tweak(self
, pname
, typ
, txt
):
462 def mk_plic(self
, inum
, irq_offs
):
464 print "mk_plic", self
.name
, inum
, irq_offs
465 niq
= self
.num_irqs()
467 return ('', irq_offs
)
468 name
= self
.get_iname(inum
)
469 res
.append("// PLIC rules for {0}".format(name
))
470 for idx
in range(niq
):
471 plic_obj
= self
.plic_object(name
, idx
)
472 print "plic_obj", name
, idx
, plic_obj
473 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
475 irq_offs
+= 1 # increment to next irq
476 return ('\n'.join(res
), irq_offs
)
478 def mk_ext_ifacedef(self
, iname
, inum
):
481 def extfastifinstance(self
, name
, count
):
484 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
488 pname
= self
.get_iname(count
)
492 sname
= self
.peripheral
.iname().format(count
)
493 template
= "interface {0}{3} = {2}{1}{4};"
494 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
496 def extifinstance2(self
, name
, count
):
499 def extifinstance(self
, name
, count
):
500 return self
._extifinstance
(name
, count
, "",
501 "pinmux.peripheral_side.")
505 rule rl_connect_{0}_to_plic_{2};
506 if({1} == 1'b1) begin
507 ff_gateway_queue[{2}].enq(1);
508 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
513 axi_master_declarations
= """\
514 typedef 0 Dmem_master_num;
515 typedef 1 Imem_master_num;
517 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
519 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
521 typedef TAdd#(DMA_master_num,1)
525 axi_fastslave_declarations
= """\
527 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
528 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
530 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
532 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
534 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
536 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
538 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
539 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
541 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
544 axi_slave_declarations
= """\
545 typedef 0 SlowMaster;
547 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
549 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
551 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
553 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
556 pinmux_cellrule
= """\
557 rule connect_select_lines_pinmux;
563 class CallFn(object):
564 def __init__(self
, peripheral
, name
):
565 self
.peripheral
= peripheral
568 def __call__(self
, *args
):
569 #print "__call__", self.name, self.peripheral.slow, args
570 if not self
.peripheral
.slow
:
572 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
575 class PeripheralIface(object):
576 def __init__(self
, ifacename
):
578 slow
= slowfactory
.getcls(ifacename
)
579 print "Iface", ifacename
, slow
581 self
.slow
= slow(ifacename
)
582 self
.slow
.peripheral
= self
583 for fname
in ['slowimport',
585 'extifinstance2', 'extifinstance', 'extifdecl',
586 'slowifdecl', 'slowifdeclmux',
589 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
591 'mk_plic', 'mk_ext_ifacedef',
592 '_mk_clk_con', 'mk_ext_ifacedef',
593 'mk_connection', 'mk_master_connection',
594 'mk_cellconn', '_mk_pincon']:
595 fn
= CallFn(self
, fname
)
596 setattr(self
, fname
, types
.MethodType(fn
, self
))
598 #print "PeripheralIface"
601 def mksuffix(self
, name
, i
):
602 if self
.slow
is None:
604 return self
.slow
.mksuffix(name
, i
)
606 def axi_reg_def(self
, start
, count
):
609 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
611 def axi_master_idx(self
, start
, count
, typ
):
612 if not self
.slow
or not self
.slow
.has_axi_master():
614 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
616 def axi_slave_idx(self
, start
, count
, typ
):
619 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
621 def axi_fastaddr_map(self
, count
):
624 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
626 def axi_addr_map(self
, count
):
629 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
632 class PeripheralInterfaces(object):
634 self
.fastbusmode
= False
636 def slowimport(self
, *args
):
638 for (name
, count
) in self
.ifacecount
:
639 #print "slowimport", name, self.data[name].slowimport
640 ret
.append(self
.data
[name
].slowimport())
641 return '\n'.join(li(list(filter(None, ret
)), 4))
643 def extfastifinstance(self
, *args
):
645 for (name
, count
) in self
.ifacecount
:
646 for i
in range(count
):
647 iname
= self
.data
[name
].iname().format(i
)
648 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
649 if self
.is_on_fastbus(name
, i
):
651 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
652 return '\n'.join(li(list(filter(None, ret
)), 8))
654 def extifinstance2(self
, *args
):
656 for (name
, count
) in self
.ifacecount
:
657 for i
in range(count
):
658 iname
= self
.data
[name
].iname().format(i
)
659 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
660 return '\n'.join(li(list(filter(None, ret
)), 8))
662 def extifinstance(self
, *args
):
664 for (name
, count
) in self
.ifacecount
:
665 for i
in range(count
):
666 iname
= self
.data
[name
].iname().format(i
)
667 if not self
.is_on_fastbus(name
, i
):
669 ret
.append(self
.data
[name
].extifinstance(name
, i
))
670 return '\n'.join(li(list(filter(None, ret
)), 8))
672 def extifdecl(self
, *args
):
674 for (name
, count
) in self
.ifacecount
:
675 for i
in range(count
):
676 if not self
.is_on_fastbus(name
, i
):
678 ret
.append(self
.data
[name
].extifdecl(name
, i
))
679 return '\n'.join(li(list(filter(None, ret
)), 8))
681 def slowifdeclmux(self
, *args
):
683 for (name
, count
) in self
.ifacecount
:
684 for i
in range(count
):
685 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
686 return '\n'.join(li(list(filter(None, ret
)), 8))
688 def fastifdecl(self
, *args
):
690 for (name
, count
) in self
.ifacecount
:
691 for i
in range(count
):
692 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
693 if self
.is_on_fastbus(name
, i
):
695 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
696 return '\n'.join(li(list(filter(None, ret
)), 4))
698 def slowifdecl(self
, *args
):
700 for (name
, count
) in self
.ifacecount
:
701 for i
in range(count
):
702 if self
.is_on_fastbus(name
, i
):
704 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
705 return '\n'.join(list(filter(None, ret
)))
707 def axi_fastmem_def(self
, *args
):
708 return self
._axi
_reg
_def
(0x50000000, *args
)
710 def axi_reg_def(self
, *args
):
711 return self
._axi
_reg
_def
(0x00011100, *args
)
713 def _axi_reg_def(self
, start
, *args
):
715 for (name
, count
) in self
.ifacecount
:
716 for i
in range(count
):
717 if self
.is_on_fastbus(name
, i
):
719 x
= self
.data
[name
].axi_reg_def(start
, i
)
720 #print ("ifc", name, x)
724 return '\n'.join(list(filter(None, ret
)))
726 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
728 for (name
, count
) in self
.ifacecount
:
729 for i
in range(count
):
730 if self
.is_on_fastbus(name
, i
):
733 fn
= self
.data
[name
].axi_master_idx
735 fn
= self
.data
[name
].axi_slave_idx
736 (rdef
, offs
) = fn(start
, i
, idxtype
)
737 #print ("ifc", name, rdef, offs)
740 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
741 decls
= '\n'.join(list(filter(None, ret
)))
742 return template
.format(decls
)
744 def axi_slave_idx(self
, *args
):
745 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
748 def axi_fastslave_idx(self
, *args
):
749 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
752 def axi_master_idx(self
, *args
):
753 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
756 def axi_fastslave_idx(self
, *args
):
757 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
760 def axi_fastaddr_map(self
, *args
):
762 for (name
, count
) in self
.ifacecount
:
763 for i
in range(count
):
764 if self
.is_on_fastbus(name
, i
):
766 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
767 return '\n'.join(li(list(filter(None, ret
)), 8))
769 def axi_addr_map(self
, *args
):
771 for (name
, count
) in self
.ifacecount
:
772 for i
in range(count
):
773 if self
.is_on_fastbus(name
, i
):
775 ret
.append(self
.data
[name
].axi_addr_map(i
))
776 return '\n'.join(li(list(filter(None, ret
)), 8))
778 def mkfast_peripheral(self
, *args
):
780 for (name
, count
) in self
.ifacecount
:
781 for i
in range(count
):
782 if self
.is_on_fastbus(name
, i
):
784 #print "mkfast", name, count
785 x
= self
.data
[name
].mkfast_peripheral()
787 suffix
= self
.data
[name
].mksuffix(name
, i
)
788 ret
.append(x
.format(suffix
))
789 return '\n'.join(li(list(filter(None, ret
)), 8))
791 def mkslow_peripheral(self
, *args
):
793 for (name
, count
) in self
.ifacecount
:
794 for i
in range(count
):
795 if self
.is_on_fastbus(name
, i
):
797 #print "mkslow", name, count
798 x
= self
.data
[name
].mkslow_peripheral()
800 suffix
= self
.data
[name
].mksuffix(name
, i
)
801 ret
.append(x
.format(suffix
))
802 return '\n'.join(li(list(filter(None, ret
)), 8))
804 def _mk_connection(self
, fabric
, typ
, indent
, master
, *args
):
806 for (name
, count
) in self
.ifacecount
:
807 for i
in range(count
):
808 if self
.is_on_fastbus(name
, i
):
811 txt
= self
.data
[name
].mk_master_connection(i
, fabric
, typ
)
813 txt
= self
.data
[name
].mk_connection(i
, fabric
, typ
)
817 return '\n'.join(li(list(filter(None, ret
)), indent
))
819 def mk_master_connection(self
, *args
):
820 return self
._mk
_connection
("fabric", "fast", 8, True, *args
)
822 def mk_fast_connection(self
, *args
):
823 return self
._mk
_connection
("fabric", "fast", 12, False, *args
)
825 def mk_connection(self
, *args
):
826 return self
._mk
_connection
("slow_fabric", "", 8, False, *args
)
828 def mk_cellconn(self
):
831 for (name
, count
) in self
.ifacecount
:
832 for i
in range(count
):
833 if self
.is_on_fastbus(name
, i
):
835 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
838 (txt
, cellcount
) = res
840 ret
= li('\n'.join(list(filter(None, ret
))), 4)
841 return li(pinmux_cellrule
.format(ret
), 4)
844 return self
._mk
_pincon
("slow")
846 def mk_fast_pincon(self
):
847 return self
._mk
_pincon
("fast")
849 def _mk_pincon(self
, typ
):
851 for (name
, count
) in self
.ifacecount
:
852 for i
in range(count
):
853 if self
.is_on_fastbus(name
, i
):
855 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
857 return '\n'.join(li(list(filter(None, ret
)), 4))
859 def mk_dma_irq(self
):
867 for (name
, count
) in self
.ifacecount
:
869 for i
in range(count
):
870 if not self
.is_on_fastbus(name
, i
):
872 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
876 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
877 ifacerules
.append(txt
)
878 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
880 ifacerules
= list(filter(None, ifacerules
))
882 txt
= "rule synchronize_%s_interrupts;" % name
885 rules
.append("endrule")
887 cnct
= list(filter(None, cnct
))
889 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
890 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
893 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
895 cnct
.append(" dma.interrupt_from_peripherals(\n" +
896 " lv_interrupt_to_DMA);")
897 cnct
.append("endrule;")
899 ret
= list(filter(None, sync
+ rules
+ cnct
))
901 return '\n'.join(ret
)
903 def num_dmachannels(self
):
904 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
906 def mk_ext_ifacedef(self
):
908 for (name
, count
) in self
.ifacecount
:
909 for i
in range(count
):
910 if self
.is_on_fastbus(name
, i
):
912 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
914 return '\n'.join(li(list(filter(None, ret
)), 8))
918 irq_offs
= 8 # XXX: DMA scovers 0-7?
919 for (name
, count
) in self
.ifacecount
:
920 for i
in range(count
):
921 if self
.is_on_fastbus(name
, i
):
923 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
926 (txt
, irq_offs
) = res
928 self
.num_slow_irqs
= irq_offs
929 return '\n'.join(li(list(filter(None, ret
)), 4))
931 def mk_sloirqsdef(self
):
932 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
934 def mk_fastclk_con(self
):
935 return self
._mk
_clk
_con
("fast")
937 def mk_slowclk_con(self
):
938 return self
._mk
_clk
_con
("slow")
940 def _mk_clk_con(self
, ctype
):
942 for (name
, count
) in self
.ifacecount
:
943 for i
in range(count
):
944 if self
.is_on_fastbus(name
, i
):
946 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
948 return '\n'.join(li(list(filter(None, ret
)), 8))
950 def is_on_fastbus(self
, name
, i
):
951 #print "fastbus mode", self.fastbusmode, name, i
952 iname
= self
.data
[name
].iname().format(i
)
954 return iname
not in self
.fastbus
955 return iname
in self
.fastbus
958 class PFactory(object):
959 def getcls(self
, name
):
960 from uart
import uart
961 from quart
import quart
962 from sdmmc
import sdmmc
964 from eint
import eint
965 from rs232
import rs232
967 from eint
import eint
968 from jtag
import jtag
969 from spi
import spi
, mspi
970 from qspi
import qspi
, mqspi
971 from gpio
import gpio
972 from rgbttl
import rgbttl
973 from flexbus
import flexbus
974 from sdram
import sdram
976 for k
, v
in {'uart': uart
,
993 if name
.startswith(k
):
998 slowfactory
= PFactory()
1000 if __name__
== '__main__':
1002 print p
.slowimport()
1003 print p
.slowifdecl()
1004 i
= PeripheralIface('uart')
1006 i
= PeripheralIface('gpioa')