src/decoder/test/test_power_decoder.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import sys
   6 import os
   7 import unittest
   8 sys.path.append("../")
   9 from power_decoder import (PowerDecoder)
  10 from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
  11                          OutSel, RC, LdstLen, CryIn, single_bit_flags,
  12                          get_signal_name, get_csv)
  13
  14
  15 class DecoderTestCase(FHDLTestCase):
  16
  17     def run_tst(self, width, csvname, suffix=None, opint=True):
  18         m = Module()
  19         comb = m.d.comb
  20         opcode = Signal(width)
  21         function_unit = Signal(Function)
  22         internal_op = Signal(InternalOp)
  23         in1_sel = Signal(In1Sel)
  24         in2_sel = Signal(In2Sel)
  25         in3_sel = Signal(In3Sel)
  26         out_sel = Signal(OutSel)
  27         rc_sel = Signal(RC)
  28         ldst_len = Signal(LdstLen)
  29         cry_in = Signal(CryIn)
  30
  31         opcodes = get_csv(csvname)
  32         m.submodules.dut = dut = PowerDecoder(width, opcodes, opint, suffix=suffix)
  33         comb += [dut.opcode_in.eq(opcode),
  34                  function_unit.eq(dut.op.function_unit),
  35                  in1_sel.eq(dut.op.in1_sel),
  36                  in2_sel.eq(dut.op.in2_sel),
  37                  in3_sel.eq(dut.op.in3_sel),
  38                  out_sel.eq(dut.op.out_sel),
  39                  rc_sel.eq(dut.op.rc_sel),
  40                  ldst_len.eq(dut.op.ldst_len),
  41                  cry_in.eq(dut.op.cry_in),
  42                  internal_op.eq(dut.op.internal_op)]
  43
  44         sim = Simulator(m)
  45
  46         def process():
  47             for row in dut.opcodes:
  48                 if not row['unit']:
  49                     continue
  50                 op = row['opcode']
  51                 if not opint: # HACK: convert 001---10 to 0b00100010
  52                     op = "0b" + op.replace('-', '0')
  53                 print ("opint", opint, row['opcode'], op)
  54                 yield opcode.eq(int(op, 0))
  55                 yield Delay(1e-6)
  56                 signals = [(function_unit, Function, 'unit'),
  57                            (internal_op, InternalOp, 'internal op'),
  58                            (in1_sel, In1Sel, 'in1'),
  59                            (in2_sel, In2Sel, 'in2'),
  60                            (in3_sel, In3Sel, 'in3'),
  61                            (out_sel, OutSel, 'out'),
  62                            (rc_sel, RC, 'rc'),
  63                            (cry_in, CryIn, 'cry in'),
  64                            (ldst_len, LdstLen, 'ldst len')]
  65                 for sig, enm, name in signals:
  66                     result = yield sig
  67                     expected = enm[row[name]]
  68                     msg = f"{sig.name} == {enm(result)}, expected: {expected}"
  69                     self.assertEqual(enm(result), expected, msg)
  70                 for bit in single_bit_flags:
  71                     sig = getattr(dut.op, get_signal_name(bit))
  72                     result = yield sig
  73                     expected = int(row[bit])
  74                     msg = f"{sig.name} == {result}, expected: {expected}"
  75                     self.assertEqual(expected, result, msg)
  76         sim.add_process(process)
  77         with sim.write_vcd("test.vcd", "test.gtkw", traces=[
  78                 opcode, function_unit, internal_op,
  79                 in1_sel, in2_sel]):
  80             sim.run()
  81
  82     def generate_ilang(self, width, csvname, opint=True, suffix=None):
  83         prefix = os.path.splitext(csvname)[0]
  84         if suffix:
  85             prefix += ".%s" % str(suffix).replace(" ", "")[1:-1]
  86         dut = PowerDecoder(width, get_csv(csvname), opint, suffix=suffix)
  87         vl = rtlil.convert(dut, ports=dut.ports())
  88         with open("%s_decoder.il" % prefix, "w") as f:
  89             f.write(vl)
  90
  91     def test_major(self):
  92         self.run_tst(6, "major.csv")
  93         self.generate_ilang(6, "major.csv")
  94
  95     def test_minor_19(self):
  96         self.run_tst(10, "minor_19.csv", suffix=(0, 5))
  97         self.generate_ilang(10, "minor_19.csv", suffix=(0, 5))
  98
  99     def test_minor_19_00000(self):
 100         self.run_tst(10, "minor_19_00000.csv")
 101         self.generate_ilang(10, "minor_19_00000.csv")
 102
 103     def test_minor_30(self):
 104         self.run_tst(4, "minor_30.csv")
 105         self.generate_ilang(4, "minor_30.csv")
 106
 107     def test_minor_31(self):
 108         self.run_tst(10, "minor_31.csv", suffix=(0, 5))
 109         self.generate_ilang(10, "minor_31.csv", suffix=(0, 5))
 110
 111     #def test_minor_31_prefix(self):
 112     #    self.run_tst(10, "minor_31.csv", suffix=(5, 10))
 113     #    self.generate_ilang(10, "minor_31.csv", suffix=(5, 10))
 114
 115     def test_extra(self):
 116         self.run_tst(32, "extra.csv", opint=False)
 117         self.generate_ilang(32, "extra.csv", opint=False)
 118
 119
 120 if __name__ == "__main__":
 121     unittest.main()