1 from nmigen
import Elaboratable
, Signal
, Module
, Const
, Mux
2 from nmigen
.cli
import main
3 from nmigen
.cli
import verilog
, rtlil
8 class Adder(Elaboratable
):
9 def __init__(self
, width
):
10 self
.a
= Signal(width
)
11 self
.b
= Signal(width
)
12 self
.o
= Signal(width
)
14 def elaborate(self
, platform
):
16 m
.d
.comb
+= self
.o
.eq(self
.a
+ self
.b
)
20 class Subtractor(Elaboratable
):
21 def __init__(self
, width
):
22 self
.a
= Signal(width
)
23 self
.b
= Signal(width
)
24 self
.o
= Signal(width
)
26 def elaborate(self
, platform
):
28 m
.d
.comb
+= self
.o
.eq(self
.a
- self
.b
)
32 class Multiplier(Elaboratable
):
33 def __init__(self
, width
):
34 self
.a
= Signal(width
)
35 self
.b
= Signal(width
)
36 self
.o
= Signal(width
)
38 def elaborate(self
, platform
):
40 m
.d
.comb
+= self
.o
.eq(self
.a
* self
.b
)
44 class Shifter(Elaboratable
):
45 def __init__(self
, width
):
47 self
.a
= Signal(width
)
48 self
.b
= Signal(width
)
49 self
.o
= Signal(width
)
51 def elaborate(self
, platform
):
53 btrunc
= Signal(self
.width
)
54 m
.d
.comb
+= btrunc
.eq(self
.b
& Const((1<<self
.width
)-1))
55 m
.d
.comb
+= self
.o
.eq(self
.a
>> btrunc
)
59 class ALU(Elaboratable
):
60 def __init__(self
, width
):
62 self
.a
= Signal(width
)
63 self
.b
= Signal(width
)
64 self
.o
= Signal(width
)
67 def elaborate(self
, platform
):
69 add
= Adder(self
.width
)
70 sub
= Subtractor(self
.width
)
71 mul
= Multiplier(self
.width
)
72 shf
= Shifter(self
.width
)
74 m
.submodules
.add
= add
75 m
.submodules
.sub
= sub
76 m
.submodules
.mul
= mul
77 m
.submodules
.shf
= shf
78 for mod
in [add
, sub
, mul
, shf
]:
83 with m
.Switch(self
.op
):
84 for i
, mod
in enumerate([add
, sub
, mul
, shf
]):
86 m
.d
.comb
+= self
.o
.eq(mod
.o
)
99 class BranchOp(Elaboratable
):
100 def __init__(self
, width
, op
):
101 self
.a
= Signal(width
)
102 self
.b
= Signal(width
)
103 self
.o
= Signal(width
)
106 def elaborate(self
, platform
):
108 m
.d
.comb
+= self
.o
.eq(Mux(self
.op(self
.a
, self
.b
), 1, 0))
112 class BranchALU(Elaboratable
):
113 def __init__(self
, width
):
115 self
.a
= Signal(width
)
116 self
.b
= Signal(width
)
117 self
.o
= Signal(width
)
120 def elaborate(self
, platform
):
122 bgt
= BranchOp(self
.width
, operator
.gt
)
123 blt
= BranchOp(self
.width
, operator
.lt
)
124 beq
= BranchOp(self
.width
, operator
.eq
)
125 bne
= BranchOp(self
.width
, operator
.ne
)
127 m
.submodules
.bgt
= bgt
128 m
.submodules
.blt
= blt
129 m
.submodules
.beq
= beq
130 m
.submodules
.bne
= bne
131 for mod
in [bgt
, blt
, beq
, bne
]:
136 with m
.Switch(self
.op
):
137 for i
, mod
in enumerate([bgt
, blt
, beq
, bne
]):
139 m
.d
.comb
+= self
.o
.eq(mod
.o
)
152 if __name__
== "__main__":
154 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
155 with
open("test_alu.il", "w") as f
:
158 alu
= BranchALU(width
=16)
159 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
160 with
open("test_branch_alu.il", "w") as f
: