1 from nmigen
import Elaboratable
, Signal
, Module
2 from nmigen
.cli
import main
5 class Adder(Elaboratable
):
6 def __init__(self
, width
):
11 def elaborate(self
, platform
):
13 m
.d
.comb
+= self
.o
.eq(self
.a
+ self
.b
)
17 class Subtractor(Elaboratable
):
18 def __init__(self
, width
):
19 self
.a
= Signal(width
)
20 self
.b
= Signal(width
)
21 self
.o
= Signal(width
)
23 def elaborate(self
, platform
):
25 m
.d
.comb
+= self
.o
.eq(self
.a
- self
.b
)
29 class Multiplier(Elaboratable
):
30 def __init__(self
, width
):
31 self
.a
= Signal(width
)
32 self
.b
= Signal(width
)
33 self
.o
= Signal(width
)
35 def elaborate(self
, platform
):
37 m
.d
.comb
+= self
.o
.eq(self
.a
* self
.b
)
41 class Shifter(Elaboratable
):
42 def __init__(self
, width
):
43 self
.a
= Signal(width
)
44 self
.b
= Signal(max=width
)
45 self
.o
= Signal(width
)
47 def elaborate(self
, platform
):
49 m
.d
.comb
+= self
.o
.eq(self
.a
<< self
.b
)
53 class ALU(Elaboratable
):
54 def __init__(self
, width
):
56 self
.a
= Signal(width
)
57 self
.b
= Signal(width
)
58 self
.o
= Signal(width
)
61 def elaborate(self
, platform
):
63 add
= Adder(self
.width
)
64 sub
= Subtractor(self
.width
)
65 mul
= Multiplier(self
.width
)
66 shf
= Shifter(self
.width
)
68 m
.submodules
.add
= add
69 m
.submodules
.sub
= sub
70 m
.submodules
.mul
= mul
71 m
.submodules
.shf
= shf
72 for mod
in [add
, sub
, mul
, shf
]:
77 with m
.Switch(self
.op
):
79 m
.d
.comb
+= self
.o
.eq(add
.o
)
81 m
.d
.comb
+= self
.o
.eq(sub
.o
)
83 m
.d
.comb
+= self
.o
.eq(mul
.o
)
85 m
.d
.comb
+= self
.o
.eq(shf
.o
)
89 if __name__
== "__main__":
91 main(alu
, ports
=[alu
.op
, alu
.a
, alu
.b
, alu
.o
])