src/experiment/cscore.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Array, Cat, Elaboratable
   4
   5 from regfile.regfile import RegFileArray
   6 from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit
   7 from scoreboard.fu_fu_matrix import FUFUDepMatrix
   8 from scoreboard.fu_reg_matrix import FURegDepMatrix
   9 from scoreboard.global_pending import GlobalPending
  10 from scoreboard.group_picker import GroupPicker
  11 from scoreboard.issue_unit import IntFPIssueUnit
  12
  13
  14 from alu_hier import Adder, Subtractor
  15
  16 class Scoreboard(Elaboratable):
  17     def __init__(self, rwid, n_regs):
  18         """ Inputs:
  19
  20             * :rwid:   bit width of register file(s) - both FP and INT
  21             * :n_regs: depth of register file(s) - number of FP and INT regs
  22         """
  23         self.rwid = rwid
  24         self.n_regs = n_regs
  25
  26         # inputs
  27         self.int_store_i = Signal(reset_less=True) # instruction is a store
  28         self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
  29         self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
  30         self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
  31
  32         # Register Files
  33         self.intregs = RegFileArray(rwid, n_regs)
  34         self.int_dest = self.intregs.write_port("dest")
  35         self.int_src1 = self.intregs.read_port("src1")
  36         self.int_src2 = self.intregs.read_port("src2")
  37
  38         self.fpregs = RegFileArray(rwid, n_regs)
  39         self.fp_dest = self.fpregs.write_port("dest")
  40         self.fp_src1 = self.fpregs.read_port("src1")
  41         self.fp_src2 = self.fpregs.read_port("src2")
  42
  43     def elaborate(self, platform):
  44         m = Module()
  45         m.submodules.intregs = self.intregs
  46         m.submodules.fpregs = self.fpregs
  47
  48         # Int ALUs
  49         m.submodules.adder = adder = Adder(self.rwid)
  50         m.submodules.subtractor = subtractor = Subtractor(self.rwid)
  51         int_alus = [adder, subtractor]
  52
  53         # Int FUs
  54         il = []
  55         int_rd_pend_v = []
  56         int_wr_pend_v = []
  57         for i, a in enumerate(int_alus):
  58             # set up Integer Function Unit, add to module (and python list)
  59             fu = IntFnUnit(self.rwid, shadow_wid=0)
  60             setattr(m.submodules, "intfu%d" % i, fu)
  61             il.append(fu)
  62             # collate the read/write pending vectors (to go into global pending)
  63             int_rd_pend_v.append(fu.int_rd_pend_o)
  64             int_wr_pend_v.append(fu.int_wr_pend_o)
  65         int_fus = Array(il)
  66
  67         # Count of number of FUs
  68         n_int_fus = len(il)
  69         n_fp_fus = 0 # for now
  70
  71         n_fus = n_int_fus + n_fp_fus # plus FP FUs
  72
  73         # Integer FU-FU Dep Matrix
  74         m.submodules.intfudeps = intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
  75
  76         # Integer FU-Reg Dep Matrix
  77         intregdeps = FUFUDepMatrix(self.n_regs, n_int_fus)
  78         m.submodules.intregdeps = intregdeps
  79
  80         # Integer Priority Picker 1: Adder + Subtractor
  81         intpick1 = GroupPicker(2) # picks between add and sub
  82         m.submodules.intpick1 = intpick1
  83
  84         # Global Pending Vectors (INT and FP)
  85         # NOTE: number of vectors is NOT same as number of FUs.
  86         g_int_rd_pend_v = GlobalPending(self.rwid, int_rd_pend_v)
  87         g_int_wr_pend_v = GlobalPending(self.rwid, int_wr_pend_v)
  88         m.submodules.g_int_rd_pend_v = g_int_rd_pend_v
  89         m.submodules.g_int_wr_pend_v = g_int_wr_pend_v
  90
  91         # INT/FP Issue Unit
  92         issueunit = IntFPIssueUnit(self.rwid, n_int_fus, n_fp_fus)
  93         m.submodules.issueunit = issueunit
  94
  95         #---------
  96         # ok start wiring things together...
  97         # "now hear de word of de looord... dem bones dem bones dem dryy bones"
  98         # https://www.youtube.com/watch?v=pYb8Wm6-QfA
  99         #---------
 100
 101         #---------
 102         # Issue Unit is where it starts.  set up some in/outs for this module
 103         #---------
 104         m.d.comb += [issueunit.i.store_i.eq(self.int_store_i),
 105                      issueunit.i.dest_i.eq(self.int_dest_i),
 106                      issueunit.i.src1_i.eq(self.int_src1_i),
 107                      issueunit.i.src2_i.eq(self.int_src2_i)
 108                     ]
 109         self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
 110
 111         # connect global rd/wr pending vectors
 112         m.d.comb += issueunit.i.g_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
 113         # TODO: issueunit.f (FP)
 114
 115         # and int function issue / busy arrays, and dest/src1/src2
 116         fissue_l = []
 117         fbusy_l = []
 118         for i, fu in enumerate(il):
 119             fissue_l.append(fu.issue_i)
 120             fbusy_l.append(fu.busy_o)
 121             m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
 122             m.d.comb += fu.dest_i.eq(issueunit.i.dest_i)
 123             m.d.comb += fu.src1_i.eq(issueunit.i.src1_i)
 124             m.d.comb += fu.src2_i.eq(issueunit.i.src2_i)
 125             m.d.comb += issueunit.i.busy_i[i].eq(fu.busy_o)
 126
 127         #---------
 128         # connect Function Units
 129         #---------
 130
 131         return m
 132
 133
 134     def __iter__(self):
 135         yield from self.intregs
 136         yield from self.fpregs
 137         #yield from self.int_src1
 138         #yield from self.int_dest
 139         #yield from self.int_src1
 140         #yield from self.int_src2
 141         #yield from self.fp_dest
 142         #yield from self.fp_src1
 143         #yield from self.fp_src2
 144
 145     def ports(self):
 146         return list(self)
 147
 148
 149 def scoreboard_sim(dut):
 150     yield dut.dest_i.eq(1)
 151     yield dut.issue_i.eq(1)
 152     yield
 153     yield dut.issue_i.eq(0)
 154     yield
 155     yield dut.src1_i.eq(1)
 156     yield dut.issue_i.eq(1)
 157     yield
 158     yield
 159     yield
 160     yield dut.issue_i.eq(0)
 161     yield
 162     yield dut.go_read_i.eq(1)
 163     yield
 164     yield dut.go_read_i.eq(0)
 165     yield
 166     yield dut.go_write_i.eq(1)
 167     yield
 168     yield dut.go_write_i.eq(0)
 169     yield
 170
 171 def test_scoreboard():
 172     dut = Scoreboard(32, 8)
 173     vl = rtlil.convert(dut, ports=dut.ports())
 174     with open("test_scoreboard.il", "w") as f:
 175         f.write(vl)
 176
 177     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_scoreboard.vcd')
 178
 179 if __name__ == '__main__':
 180     test_scoreboard()