src/experiment/cscore.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Array, Elaboratable
   4
   5 from regfile.regfile import RegFileArray
   6 from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit
   7 from scoreboard.fu_fu_matrix import FUFUDepMatrix
   8
   9 from alu_hier import Adder, Subtractor
  10
  11 class Scoreboard(Elaboratable):
  12     def __init__(self, reg_width, reg_depth):
  13         self.reg_width = reg_width
  14         self.reg_depth = reg_depth
  15
  16         # Register Files
  17         self.intregs = RegFileArray(reg_width, reg_depth)
  18         self.int_dest = self.intregs.write_port()
  19         self.int_src1 = self.intregs.read_port()
  20         self.int_src2 = self.intregs.read_port()
  21
  22         self.fpregs = RegFileArray(reg_width, reg_depth)
  23         self.fp_dest = self.fpregs.write_port()
  24         self.fp_src1 = self.fpregs.read_port()
  25         self.fp_src2 = self.fpregs.read_port()
  26
  27     def elaborate(self, platform):
  28         m = Module()
  29         m.submodules.intregs = self.intregs
  30         m.submodules.fpregs = self.fpregs
  31
  32         # Int ALUs
  33         m.submodules.adder = adder = Adder(self.reg_width)
  34         m.submodules.subtractor = subtractor = Subtractor(self.reg_width)
  35         int_alus = [adder, subtractor]
  36
  37         # Int FUs
  38         il = []
  39         for i, a in enumerate(int_alus):
  40             fu = IntFnUnit(self.reg_width, shadow_wid=0)
  41             setattr(m.submodules, "intfu%d" % i, fu)
  42             il.append(fu)
  43         int_fus = Array(il)
  44
  45         n_fus = len(il)
  46
  47         # FU Dep Matrix
  48         m.submodules.fudeps = fudeps = FUFUDepMatrix(n_fus, n_fus)
  49
  50
  51         return m
  52
  53     def __iter__(self):
  54         yield from self.intregs
  55         yield from self.fpregs
  56         #yield from self.int_src1
  57         #yield from self.int_dest
  58         #yield from self.int_src1
  59         #yield from self.int_src2
  60         #yield from self.fp_dest
  61         #yield from self.fp_src1
  62         #yield from self.fp_src2
  63
  64     def ports(self):
  65         return list(self)
  66
  67
  68 def scoreboard_sim(dut):
  69     yield dut.dest_i.eq(1)
  70     yield dut.issue_i.eq(1)
  71     yield
  72     yield dut.issue_i.eq(0)
  73     yield
  74     yield dut.src1_i.eq(1)
  75     yield dut.issue_i.eq(1)
  76     yield
  77     yield
  78     yield
  79     yield dut.issue_i.eq(0)
  80     yield
  81     yield dut.go_read_i.eq(1)
  82     yield
  83     yield dut.go_read_i.eq(0)
  84     yield
  85     yield dut.go_write_i.eq(1)
  86     yield
  87     yield dut.go_write_i.eq(0)
  88     yield
  89
  90 def test_scoreboard():
  91     dut = Scoreboard(32, 8)
  92     vl = rtlil.convert(dut, ports=dut.ports())
  93     with open("test_scoreboard.il", "w") as f:
  94         f.write(vl)
  95
  96     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_scoreboard.vcd')
  97
  98 if __name__ == '__main__':
  99     test_scoreboard()