1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Const
, Signal
, Array
, Cat
, Elaboratable
5 from regfile
.regfile
import RegFileArray
, treereduce
6 from scoreboard
.fn_unit
import IntFnUnit
, FPFnUnit
, LDFnUnit
, STFnUnit
7 from scoreboard
.fu_fu_matrix
import FUFUDepMatrix
8 from scoreboard
.fu_reg_matrix
import FURegDepMatrix
9 from scoreboard
.global_pending
import GlobalPending
10 from scoreboard
.group_picker
import GroupPicker
11 from scoreboard
.issue_unit
import IntFPIssueUnit
, RegDecode
13 from compalu
import ComputationUnitNoDelay
15 from alu_hier
import ALU
16 from nmutil
.latch
import SRLatch
18 from random
import randint
20 class CompUnits(Elaboratable
):
22 def __init__(self
, rwid
, n_units
):
25 * :rwid: bit width of register file(s) - both FP and INT
26 * :n_units: number of ALUs
28 self
.n_units
= n_units
31 self
.issue_i
= Signal(n_units
, reset_less
=True)
32 self
.go_rd_i
= Signal(n_units
, reset_less
=True)
33 self
.go_wr_i
= Signal(n_units
, reset_less
=True)
34 self
.req_rel_o
= Signal(n_units
, reset_less
=True)
36 self
.dest_o
= Signal(rwid
, reset_less
=True)
37 self
.src1_data_i
= Signal(rwid
, reset_less
=True)
38 self
.src2_data_i
= Signal(rwid
, reset_less
=True)
40 def elaborate(self
, platform
):
46 m
.submodules
.comp1
= comp1
= ComputationUnitNoDelay(self
.rwid
, 1, add
)
47 m
.submodules
.comp2
= comp2
= ComputationUnitNoDelay(self
.rwid
, 1, sub
)
48 int_alus
= [comp1
, comp2
]
50 m
.d
.comb
+= comp1
.oper_i
.eq(Const(0)) # temporary/experiment: op=add
51 m
.d
.comb
+= comp2
.oper_i
.eq(Const(1)) # temporary/experiment: op=sub
58 req_rel_l
.append(alu
.req_rel_o
)
59 go_wr_l
.append(alu
.go_wr_i
)
60 go_rd_l
.append(alu
.go_rd_i
)
61 issue_l
.append(alu
.issue_i
)
62 m
.d
.comb
+= self
.req_rel_o
.eq(Cat(*req_rel_l
))
63 m
.d
.comb
+= Cat(*go_wr_l
).eq(self
.go_wr_i
)
64 m
.d
.comb
+= Cat(*go_rd_l
).eq(self
.go_rd_i
)
65 m
.d
.comb
+= Cat(*issue_l
).eq(self
.issue_i
)
67 # connect data register input/output
69 # merge (OR) all integer FU / ALU outputs to a single value
70 # bit of a hack: treereduce needs a list with an item named "dest_o"
71 dest_o
= treereduce(int_alus
)
72 m
.d
.comb
+= self
.dest_o
.eq(dest_o
)
74 for i
, alu
in enumerate(int_alus
):
75 m
.d
.comb
+= alu
.src1_i
.eq(self
.src1_data_i
)
76 m
.d
.comb
+= alu
.src2_i
.eq(self
.src2_data_i
)
81 class Scoreboard(Elaboratable
):
82 def __init__(self
, rwid
, n_regs
):
85 * :rwid: bit width of register file(s) - both FP and INT
86 * :n_regs: depth of register file(s) - number of FP and INT regs
92 self
.intregs
= RegFileArray(rwid
, n_regs
)
93 self
.fpregs
= RegFileArray(rwid
, n_regs
)
96 self
.int_store_i
= Signal(reset_less
=True) # instruction is a store
97 self
.int_dest_i
= Signal(max=n_regs
, reset_less
=True) # Dest R# in
98 self
.int_src1_i
= Signal(max=n_regs
, reset_less
=True) # oper1 R# in
99 self
.int_src2_i
= Signal(max=n_regs
, reset_less
=True) # oper2 R# in
101 self
.issue_o
= Signal(reset_less
=True) # instruction was accepted
103 def elaborate(self
, platform
):
106 m
.submodules
.intregs
= self
.intregs
107 m
.submodules
.fpregs
= self
.fpregs
110 int_dest
= self
.intregs
.write_port("dest")
111 int_src1
= self
.intregs
.read_port("src1")
112 int_src2
= self
.intregs
.read_port("src2")
114 fp_dest
= self
.fpregs
.write_port("dest")
115 fp_src1
= self
.fpregs
.read_port("src1")
116 fp_src2
= self
.fpregs
.read_port("src2")
118 # Int ALUs and Comp Units
120 m
.submodules
.cu
= cu
= CompUnits(self
.rwid
, n_int_alus
)
128 for i
in range(n_int_alus
):
129 # set up Integer Function Unit, add to module (and python list)
130 fu
= IntFnUnit(self
.n_regs
, shadow_wid
=0)
131 setattr(m
.submodules
, "intfu%d" % i
, fu
)
133 # collate the read/write pending vectors (to go into global pending)
134 int_src1_pend_v
.append(fu
.src1_pend_o
)
135 int_src2_pend_v
.append(fu
.src2_pend_o
)
136 int_rd_pend_v
.append(fu
.int_rd_pend_o
)
137 int_wr_pend_v
.append(fu
.int_wr_pend_o
)
138 int_fus
= Array(if_l
)
140 # Count of number of FUs
141 n_int_fus
= len(if_l
)
142 n_fp_fus
= 0 # for now
144 n_fus
= n_int_fus
+ n_fp_fus
# plus FP FUs
146 # Integer FU-FU Dep Matrix
147 intfudeps
= FUFUDepMatrix(n_int_fus
, n_int_fus
)
148 m
.submodules
.intfudeps
= intfudeps
149 # Integer FU-Reg Dep Matrix
150 intregdeps
= FURegDepMatrix(n_int_fus
, self
.n_regs
)
151 m
.submodules
.intregdeps
= intregdeps
153 # Integer Priority Picker 1: Adder + Subtractor
154 intpick1
= GroupPicker(2) # picks between add and sub
155 m
.submodules
.intpick1
= intpick1
157 # Global Pending Vectors (INT and TODO FP)
158 # NOTE: number of vectors is NOT same as number of FUs.
159 g_int_src1_pend_v
= GlobalPending(self
.n_regs
, int_src1_pend_v
)
160 g_int_src2_pend_v
= GlobalPending(self
.n_regs
, int_src2_pend_v
)
161 g_int_rd_pend_v
= GlobalPending(self
.n_regs
, int_rd_pend_v
)
162 g_int_wr_pend_v
= GlobalPending(self
.n_regs
, int_wr_pend_v
)
163 m
.submodules
.g_int_src1_pend_v
= g_int_src1_pend_v
164 m
.submodules
.g_int_src2_pend_v
= g_int_src2_pend_v
165 m
.submodules
.g_int_rd_pend_v
= g_int_rd_pend_v
166 m
.submodules
.g_int_wr_pend_v
= g_int_wr_pend_v
169 regdecode
= RegDecode(self
.n_regs
)
170 m
.submodules
.regdecode
= regdecode
171 issueunit
= IntFPIssueUnit(self
.n_regs
, n_int_fus
, n_fp_fus
)
172 m
.submodules
.issueunit
= issueunit
175 # ok start wiring things together...
176 # "now hear de word of de looord... dem bones dem bones dem dryy bones"
177 # https://www.youtube.com/watch?v=pYb8Wm6-QfA
181 # Issue Unit is where it starts. set up some in/outs for this module
183 m
.d
.comb
+= [issueunit
.i
.store_i
.eq(self
.int_store_i
),
184 regdecode
.dest_i
.eq(self
.int_dest_i
),
185 regdecode
.src1_i
.eq(self
.int_src1_i
),
186 regdecode
.src2_i
.eq(self
.int_src2_i
),
187 regdecode
.enable_i
.eq(1),
188 issueunit
.i
.dest_i
.eq(regdecode
.dest_o
),
189 self
.issue_o
.eq(issueunit
.issue_o
)
191 self
.int_insn_i
= issueunit
.i
.insn_i
# enabled by instruction decode
193 # connect global rd/wr pending vectors
194 m
.d
.comb
+= issueunit
.i
.g_wr_pend_i
.eq(g_int_wr_pend_v
.g_pend_o
)
195 # TODO: issueunit.f (FP)
197 # and int function issue / busy arrays, and dest/src1/src2
200 for i
, fu
in enumerate(if_l
):
201 fn_issue_l
.append(fu
.issue_i
)
202 fn_busy_l
.append(fu
.busy_o
)
203 m
.d
.sync
+= fu
.issue_i
.eq(issueunit
.i
.fn_issue_o
[i
])
204 m
.d
.sync
+= fu
.dest_i
.eq(self
.int_dest_i
)
205 m
.d
.sync
+= fu
.src1_i
.eq(self
.int_src1_i
)
206 m
.d
.sync
+= fu
.src2_i
.eq(self
.int_src2_i
)
207 # XXX sync, so as to stop a simulation infinite loop
208 m
.d
.sync
+= issueunit
.i
.busy_i
[i
].eq(fu
.busy_o
)
210 fn_issue_o
= Signal(len(fn_issue_l
), reset_less
=True)
211 m
.d
.comb
+= fn_issue_o
.eq(Cat(*fn_issue_l
))
212 #fn_issue_o = issueunit.i.fn_issue_o
214 # connect fu-fu matrix
217 m
.d
.comb
+= intfudeps
.rd_pend_i
.eq(g_int_rd_pend_v
.g_pend_o
)
218 m
.d
.comb
+= intfudeps
.wr_pend_i
.eq(g_int_wr_pend_v
.g_pend_o
)
220 # Group Picker... done manually for now. TODO: cat array of pick sigs
221 go_rd_o
= intpick1
.go_rd_o
222 go_wr_o
= intpick1
.go_wr_o
223 go_rd_i
= intfudeps
.go_rd_i
224 go_wr_i
= intfudeps
.go_wr_i
225 m
.d
.comb
+= go_rd_i
[0].eq(go_rd_o
[0]) # add rd
226 m
.d
.comb
+= go_wr_i
[0].eq(go_wr_o
[0]) # add wr
228 m
.d
.comb
+= go_rd_i
[1].eq(go_rd_o
[1]) # sub rd
229 m
.d
.comb
+= go_wr_i
[1].eq(go_wr_o
[1]) # sub wr
231 m
.d
.comb
+= intfudeps
.issue_i
.eq(fn_issue_o
)
233 # Connect INT FU go_rd/wr
234 for i
, fu
in enumerate(if_l
):
235 m
.d
.comb
+= fu
.go_rd_i
.eq(go_rd_o
[i
])
236 m
.d
.comb
+= fu
.go_wr_i
.eq(go_wr_o
[i
])
238 # Connect INT Fn Unit global wr/rd pending
240 m
.d
.comb
+= fu
.g_int_wr_pend_i
.eq(g_int_wr_pend_v
.g_pend_o
)
241 m
.d
.comb
+= fu
.g_int_rd_pend_i
.eq(g_int_rd_pend_v
.g_pend_o
)
244 # connect fu-dep matrix
246 r_go_rd_i
= intregdeps
.go_rd_i
247 r_go_wr_i
= intregdeps
.go_wr_i
248 m
.d
.comb
+= r_go_rd_i
.eq(go_rd_o
)
249 m
.d
.comb
+= r_go_wr_i
.eq(go_wr_o
)
251 m
.d
.comb
+= intregdeps
.dest_i
.eq(regdecode
.dest_o
)
252 m
.d
.comb
+= intregdeps
.src1_i
.eq(regdecode
.src1_o
)
253 m
.d
.comb
+= intregdeps
.src2_i
.eq(regdecode
.src2_o
)
254 m
.d
.comb
+= intregdeps
.issue_i
.eq(fn_issue_o
)
258 m
.d
.sync
+= intpick1
.req_rel_i
[0].eq(cu
.req_rel_o
[0])
259 m
.d
.sync
+= intpick1
.req_rel_i
[1].eq(cu
.req_rel_o
[1])
260 int_readable_o
= intfudeps
.readable_o
261 int_writable_o
= intfudeps
.writable_o
262 m
.d
.comb
+= intpick1
.readable_i
[0].eq(int_readable_o
[0]) # add rd
263 m
.d
.comb
+= intpick1
.writable_i
[0].eq(int_writable_o
[0]) # add wr
264 m
.d
.comb
+= intpick1
.readable_i
[1].eq(int_readable_o
[1]) # sub rd
265 m
.d
.comb
+= intpick1
.writable_i
[1].eq(int_writable_o
[1]) # sub wr
268 # Connect Register File(s)
270 print ("intregdeps wen len", len(intregdeps
.dest_rsel_o
))
271 m
.d
.comb
+= int_dest
.wen
.eq(intregdeps
.dest_rsel_o
)
272 m
.d
.comb
+= int_src1
.ren
.eq(intregdeps
.src1_rsel_o
)
273 m
.d
.comb
+= int_src2
.ren
.eq(intregdeps
.src2_rsel_o
)
275 # connect ALUs to regfule
276 m
.d
.comb
+= int_dest
.data_i
.eq(cu
.dest_o
)
277 m
.d
.comb
+= cu
.src1_data_i
.eq(int_src1
.data_o
)
278 m
.d
.comb
+= cu
.src2_data_i
.eq(int_src2
.data_o
)
280 # connect ALU Computation Units
281 for i
in range(n_int_alus
):
282 m
.d
.comb
+= cu
.go_rd_i
[i
].eq(go_rd_o
[i
])
283 m
.d
.comb
+= cu
.go_wr_i
[i
].eq(go_wr_o
[i
])
284 m
.d
.comb
+= cu
.issue_i
[i
].eq(fn_issue_l
[i
])
285 m
.d
.sync
+= if_l
[i
].req_rel_i
.eq(cu
.req_rel_o
[i
]) # pipe out ready
291 yield from self
.intregs
292 yield from self
.fpregs
293 yield self
.int_store_i
294 yield self
.int_dest_i
295 yield self
.int_src1_i
296 yield self
.int_src2_i
298 #yield from self.int_src1
299 #yield from self.int_dest
300 #yield from self.int_src1
301 #yield from self.int_src2
302 #yield from self.fp_dest
303 #yield from self.fp_src1
304 #yield from self.fp_src2
313 def __init__(self
, rwidth
, nregs
):
315 self
.regs
= [0] * nregs
317 def op(self
, op
, src1
, src2
, dest
):
318 src1
= self
.regs
[src1
]
319 src2
= self
.regs
[src2
]
321 val
= (src1
+ src2
) & ((1<<(self
.rwidth
))-1)
323 val
= (src1
- src2
) & ((1<<(self
.rwidth
))-1)
324 self
.regs
[dest
] = val
326 def setval(self
, dest
, val
):
327 self
.regs
[dest
] = val
330 for i
, val
in enumerate(self
.regs
):
331 reg
= yield dut
.intregs
.regs
[i
].reg
332 okstr
= "OK" if reg
== val
else "!ok"
333 print("reg %d expected %x received %x %s" % (i
, val
, reg
, okstr
))
335 def check(self
, dut
):
336 for i
, val
in enumerate(self
.regs
):
337 reg
= yield dut
.intregs
.regs
[i
].reg
339 print("reg %d expected %x received %x\n" % (i
, val
, reg
))
340 yield from self
.dump(dut
)
343 def int_instr(dut
, alusim
, op
, src1
, src2
, dest
):
344 for i
in range(len(dut
.int_insn_i
)):
345 yield dut
.int_insn_i
[i
].eq(0)
346 yield dut
.int_dest_i
.eq(dest
)
347 yield dut
.int_src1_i
.eq(src1
)
348 yield dut
.int_src2_i
.eq(src2
)
349 yield dut
.int_insn_i
[op
].eq(1)
350 alusim
.op(op
, src1
, src2
, dest
)
353 def print_reg(dut
, rnums
):
356 reg
= yield dut
.intregs
.regs
[rnum
].reg
357 rs
.append("%x" % reg
)
358 rnums
= map(str, rnums
)
359 print ("reg %s: %s" % (','.join(rnums
), ','.join(rs
)))
362 def scoreboard_sim(dut
, alusim
):
363 yield dut
.int_store_i
.eq(0)
365 for i
in range(1, dut
.n_regs
):
366 yield dut
.intregs
.regs
[i
].reg
.eq(i
)
373 yield from int_instr(dut
, alusim
, IADD
, 4, 3, 5)
374 yield from print_reg(dut
, [3,4,5])
376 yield from int_instr(dut
, alusim
, IADD
, 5, 2, 5)
377 yield from print_reg(dut
, [3,4,5])
379 yield from int_instr(dut
, alusim
, ISUB
, 5, 1, 3)
380 yield from print_reg(dut
, [3,4,5])
382 for i
in range(len(dut
.int_insn_i
)):
383 yield dut
.int_insn_i
[i
].eq(0)
384 yield from print_reg(dut
, [3,4,5])
386 yield from print_reg(dut
, [3,4,5])
388 yield from print_reg(dut
, [3,4,5])
391 yield from alusim
.check(dut
)
394 src1
= randint(1, dut
.n_regs
-1)
395 src2
= randint(1, dut
.n_regs
-1)
397 dest
= randint(1, dut
.n_regs
-1)
399 if dest
not in [src1
, src2
]:
407 print ("random %d: %d %d %d %d\n" % (i
, op
, src1
, src2
, dest
))
408 yield from int_instr(dut
, alusim
, op
, src1
, src2
, dest
)
409 yield from print_reg(dut
, [3,4,5])
411 yield from print_reg(dut
, [3,4,5])
412 for i
in range(len(dut
.int_insn_i
)):
413 yield dut
.int_insn_i
[i
].eq(0)
420 yield from print_reg(dut
, [3,4,5])
422 yield from print_reg(dut
, [3,4,5])
427 yield from alusim
.check(dut
)
428 yield from alusim
.dump(dut
)
431 def explore_groups(dut
):
432 from nmigen
.hdl
.ir
import Fragment
433 from nmigen
.hdl
.xfrm
import LHSGroupAnalyzer
435 fragment
= dut
.elaborate(platform
=None)
436 fr
= Fragment
.get(fragment
, platform
=None)
438 groups
= LHSGroupAnalyzer()(fragment
._statements
)
443 def test_scoreboard():
444 dut
= Scoreboard(32, 8)
445 alusim
= RegSim(32, 8)
446 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
447 with
open("test_scoreboard6600.il", "w") as f
:
450 run_simulation(dut
, scoreboard_sim(dut
, alusim
),
451 vcd_name
='test_scoreboard6600.vcd')
454 if __name__
== '__main__':