src/ieee754/cordic/test/test_clz.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4
   5 from ieee754.cordic.clz import CLZ
   6 import unittest
   7 import math
   8 import random
   9
  10
  11 class CLZTestCase(FHDLTestCase):
  12     def run_test(self, inputs, width=8):
  13
  14         m = Module()
  15
  16         m.submodules.dut = dut = CLZ(width)
  17         sig_in = Signal.like(dut.sig_in)
  18         count = Signal.like(dut.lz)
  19
  20
  21         m.d.comb += [
  22             dut.sig_in.eq(sig_in),
  23             count.eq(dut.lz)]
  24
  25         sim = Simulator(m)
  26
  27         def process():
  28             for i in inputs:
  29                 yield sig_in.eq(i)
  30                 yield Delay(1e-6)
  31         sim.add_process(process)
  32         with sim.write_vcd("clz.vcd", "clz.gtkw", traces=[
  33                 sig_in, count]):
  34             sim.run()
  35
  36     def test_selected(self):
  37         inputs = [0, 15, 10, 127]
  38         self.run_test(iter(inputs), width=8)
  39
  40
  41 if __name__ == "__main__":
  42     unittest.main()