1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.test
.utils
import FHDLTestCase
5 from ieee754
.cordic
.clz
import CLZ
11 class CLZTestCase(FHDLTestCase
):
12 def run_test(self
, inputs
, width
=8):
16 m
.submodules
.dut
= dut
= CLZ(width
)
17 sig_in
= Signal
.like(dut
.sig_in
)
18 count
= Signal
.like(dut
.lz
)
22 dut
.sig_in
.eq(sig_in
),
31 sim
.add_process(process
)
32 with sim
.write_vcd("clz.vcd", "clz.gtkw", traces
=[
36 def test_selected(self
):
37 inputs
= [0, 15, 10, 127]
38 self
.run_test(iter(inputs
), width
=8)
40 def test_non_power_2(self
):
41 inputs
= [0, 128, 512]
42 self
.run_test(iter(inputs
), width
=10)
45 if __name__
== "__main__":