1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.test
.utils
import FHDLTestCase
5 from ieee754
.cordic
.fpsin_cos
import CORDIC
6 from ieee754
.fpcommon
.fpbase
import FPNumBaseRecord
7 from python_sin_cos
import run_cordic
8 from sfpy
import Float16
, Float32
14 class SinCosTestCase(FHDLTestCase
):
15 def run_test(self
, zin
=0, fracbits
=8, expected_sin
=0, expected_cos
=0):
19 m
.submodules
.dut
= dut
= CORDIC(16)
20 z
= Signal(dut
.z0
.width
)
23 sin
= Signal(dut
.sin
.shape())
24 cos
= Signal(dut
.cos
.shape())
39 yield z
.eq(zin
.get_bits())
45 for i
in range(fracbits
* 3):
48 if rdy
and not asserted
:
49 frac
= self
.get_frac(zo
, dut
.z_out
.width
- 2)
50 print(f
"{zo:x} {frac}")
51 self
.assertEqual(str(frac
), zin
.__str
__())
55 sim
.add_sync_process(process
)
56 with sim
.write_vcd("fpsin_cos.vcd", "fpsin_cos.gtkw", traces
=[
57 cos
, sin
, ready
, start
]):
60 def run_test_assert(self
, z
, fracbits
=8):
61 self
.run_test(zin
=z
, fracbits
=fracbits
)
66 self
.run_test_assert(x
)
69 # self.run_test_assert(-6)
73 z
= random
.uniform(-1, 1)
75 self
.run_test_assert(f
)
77 def get_frac(self
, value
, bits
):
78 return value
/(1 << bits
)
80 if __name__
== "__main__":