src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3 """ div/rem/sqrt/rsqrt pipeline. """
   4 from .core import (DivPipeCoreConfig, DivPipeCoreInputData,
   5                    DivPipeCoreInterstageData, DivPipeCoreOutputData)
   6
   7
   8 class DivPipeBaseData:
   9     """ input data base type for ``DivPipe``.
  10     """
  11
  12     def __init__(self, pspec):
  13         """ Create a ``DivPipeBaseData`` instance. """
  14         width = pspec['width']
  15         self.out_do_z = Signal(reset_less=True)
  16         self.oz = Signal(width, reset_less=True)
  17
  18         self.ctx = FPPipeContext(pspec)  # context: muxid, operator etc.
  19         self.muxid = self.ctx.muxid             # annoying. complicated.
  20
  21     def __iter__(self):
  22         """ Get member signals. """
  23         yield self.out_do_z
  24         yield self.oz
  25         yield from self.ctx
  26
  27     def eq(self, rhs):
  28         """ Assign member signals. """
  29         return [self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  30                 self.ctx.eq(i.ctx)]
  31
  32
  33 class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData):
  34     """ input data type for ``DivPipe``.
  35     """
  36
  37     def __init__(self, core_config):
  38         """ Create a ``DivPipeInputData`` instance. """
  39         DivPipeCoreInputData.__init__(self, core_config)
  40         DivPipeBaseData.__init__(self, pspec)  # XXX TODO args
  41         self.out_do_z = Signal(reset_less=True)
  42         self.oz = Signal(width, reset_less=True)
  43
  44         self.ctx = FPPipeContext(pspec)  # context: muxid, operator etc.
  45         self.muxid = self.ctx.muxid             # annoying. complicated.
  46
  47     def __iter__(self):
  48         """ Get member signals. """
  49         yield from DivPipeCoreInputData.__iter__(self)
  50         yield from DivPipeBaseData.__iter__(self)
  51
  52     def eq(self, rhs):
  53         """ Assign member signals. """
  54         return DivPipeBaseData.eq(self, rhs) + \
  55             DivPipeCoreInputData.eq(self, rhs)
  56
  57
  58 class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
  59     """ interstage data type for ``DivPipe``.
  60
  61     :attribute core_config: ``DivPipeCoreConfig`` instance describing the
  62         configuration to be used.
  63     """
  64
  65     def __init__(self, core_config):
  66         """ Create a ``DivPipeCoreInterstageData`` instance. """
  67         DivPipeCoreInterstageData.__init__(self, core_config)
  68         DivPipeBaseData.__init__(self, pspec)  # XXX TODO args
  69
  70     def __iter__(self):
  71         """ Get member signals. """
  72         yield from DivPipeInterstageData.__iter__(self)
  73         yield from DivPipeBaseData.__iter__(self)
  74
  75     def eq(self, rhs):
  76         """ Assign member signals. """
  77         return DivPipeBaseData.eq(self, rhs) + \
  78             DivPipeCoreInterstageData.eq(self, rhs)
  79
  80
  81 class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
  82     """ interstage data type for ``DivPipe``.
  83
  84     :attribute core_config: ``DivPipeCoreConfig`` instance describing the
  85         configuration to be used.
  86     """
  87
  88     def __init__(self, core_config):
  89         """ Create a ``DivPipeCoreOutputData`` instance. """
  90         DivPipeCoreOutputData.__init__(self, core_config)
  91         DivPipeBaseData.__init__(self, pspec)  # XXX TODO args
  92
  93     def __iter__(self):
  94         """ Get member signals. """
  95         yield from DivPipeOutputData.__iter__(self)
  96         yield from DivPipeBaseData.__iter__(self)
  97
  98     def eq(self, rhs):
  99         """ Assign member signals. """
 100         return DivPipeBaseData.eq(self, rhs) + \
 101             DivPipeCoreOutputData.eq(self, rhs)
 102
 103
 104 class DivPipeBaseStage:
 105     """ Base Mix-in for DivPipe*Stage """
 106
 107     def _elaborate(self, m, platform):
 108         m.d.comb += self.o.oz.eq(self.i.oz)
 109         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 110         m.d.comb += self.o.ctx.eq(self.i.ctx)