add WIP code for handling Slice and Cat in a unified way, supporting assignment
[ieee754fpu.git] / src / ieee754 / fcvt / test / test_fcvt_pipe_64_32.py
1 """ test of FPCVTMuxInOut
2 """
3
4 from ieee754.fcvt.pipeline import (FPCVTMuxInOut,)
5 from ieee754.fpcommon.test.case_gen import run_pipe_fp
6 from ieee754.fpcommon.test import unit_test_single
7 from ieee754.fcvt.test.fcvt_data_64_32 import regressions
8
9 from sfpy import Float64, Float32
10
11 import unittest
12
13 def fcvt_32(x):
14 return Float32(x)
15
16 class TestFClassPipe(unittest.TestCase):
17 def test_pipe_fp64_32(self):
18 dut = FPCVTMuxInOut(64, 32, 4)
19 run_pipe_fp(dut, 64, "fcvt", unit_test_single, Float64,
20 regressions, fcvt_32, 100, True)
21
22 if __name__ == '__main__':
23 unittest.main()
24