1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Elaboratable
6 from nmigen
.cli
import main
, verilog
8 from ieee754
.fpcommon
.fpbase
import FPNumBase
, FPNumBaseRecord
9 from ieee754
.fpcommon
.fpbase
import FPState
10 from ieee754
.fpcommon
.denorm
import FPSCData
11 from ieee754
.fpcommon
.getop
import FPPipeContext
14 class FPAddStage0Data
:
16 def __init__(self
, pspec
):
18 self
.z
= FPNumBaseRecord(width
, False)
19 self
.out_do_z
= Signal(reset_less
=True)
20 self
.oz
= Signal(width
, reset_less
=True)
21 self
.tot
= Signal(self
.z
.m_width
+ 4, reset_less
=True)
22 self
.ctx
= FPPipeContext(pspec
)
23 self
.muxid
= self
.ctx
.muxid
26 return [self
.z
.eq(i
.z
), self
.out_do_z
.eq(i
.out_do_z
), self
.oz
.eq(i
.oz
),
27 self
.tot
.eq(i
.tot
), self
.ctx
.eq(i
.ctx
)]
30 class FPAddStage0Mod(Elaboratable
):
32 def __init__(self
, pspec
):
38 return FPSCData(self
.pspec
, True)
41 return FPAddStage0Data(self
.pspec
)
46 def setup(self
, m
, i
):
47 """ links module to inputs and outputs
49 m
.submodules
.add0
= self
50 m
.d
.comb
+= self
.i
.eq(i
)
52 def elaborate(self
, platform
):
54 #m.submodules.add0_in_a = self.i.a
55 #m.submodules.add0_in_b = self.i.b
56 #m.submodules.add0_out_z = self.o.z
58 # store intermediate tests (and zero-extended mantissas)
59 seq
= Signal(reset_less
=True)
60 mge
= Signal(reset_less
=True)
61 am0
= Signal(len(self
.i
.a
.m
)+1, reset_less
=True)
62 bm0
= Signal(len(self
.i
.b
.m
)+1, reset_less
=True)
63 m
.d
.comb
+= [seq
.eq(self
.i
.a
.s
== self
.i
.b
.s
),
64 mge
.eq(self
.i
.a
.m
>= self
.i
.b
.m
),
65 am0
.eq(Cat(self
.i
.a
.m
, 0)),
66 bm0
.eq(Cat(self
.i
.b
.m
, 0))
68 # same-sign (both negative or both positive) add mantissas
69 with m
.If(~self
.i
.out_do_z
):
70 m
.d
.comb
+= self
.o
.z
.e
.eq(self
.i
.a
.e
)
73 self
.o
.tot
.eq(am0
+ bm0
),
74 self
.o
.z
.s
.eq(self
.i
.a
.s
)
76 # a mantissa greater than b, use a
79 self
.o
.tot
.eq(am0
- bm0
),
80 self
.o
.z
.s
.eq(self
.i
.a
.s
)
82 # b mantissa greater than a, use b
85 self
.o
.tot
.eq(bm0
- am0
),
86 self
.o
.z
.s
.eq(self
.i
.b
.s
)
89 m
.d
.comb
+= self
.o
.oz
.eq(self
.i
.oz
)
90 m
.d
.comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
91 m
.d
.comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)
95 class FPAddStage0(FPState
):
96 """ First stage of add. covers same-sign (add) and subtract
97 special-casing when mantissas are greater or equal, to
98 give greatest accuracy.
101 def __init__(self
, pspec
):
102 FPState
.__init
__(self
, "add_0")
103 self
.mod
= FPAddStage0Mod(width
)
104 self
.o
= self
.mod
.ospec()
106 def setup(self
, m
, i
):
107 """ links module to inputs and outputs
111 # NOTE: these could be done as combinatorial (merge add0+add1)
112 m
.d
.sync
+= self
.o
.eq(self
.mod
.o
)