tidyup
[ieee754fpu.git] / src / ieee754 / fpadd / addstages.py
1 """IEEE754 Floating Point Adder Pipeline
2
3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4
5 """
6
7 from nmigen import Module
8 from nmigen.cli import main, verilog
9
10 from nmutil.singlepipe import StageChain
11 from ieee754.pipeline import DynamicPipe
12
13 from ieee754.fpcommon.denorm import FPSCData
14 from ieee754.fpcommon.postcalc import FPAddStage1Data
15 from ieee754.fpadd.align import FPAddAlignSingleMod
16 from ieee754.fpadd.add0 import FPAddStage0Mod
17 from ieee754.fpadd.add1 import FPAddStage1Mod
18
19
20 class FPAddAlignSingleAdd(DynamicPipe):
21
22 def __init__(self, pspec):
23 self.pspec = pspec
24 super().__init__(pspec)
25
26 def ispec(self):
27 return FPSCData(self.pspec, True)
28
29 def ospec(self):
30 return FPAddStage1Data(self.pspec) # AddStage1 ospec
31
32 def setup(self, m, i):
33 """ links module to inputs and outputs
34 """
35
36 # chain AddAlignSingle, AddStage0 and AddStage1
37 mod = FPAddAlignSingleMod(self.pspec)
38 a0mod = FPAddStage0Mod(self.pspec)
39 a1mod = FPAddStage1Mod(self.pspec)
40
41 chain = StageChain([mod, a0mod, a1mod])
42 chain.setup(m, i)
43
44 self.o = a1mod.o
45
46 def process(self, i):
47 return self.o
48