1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
6 from nmigen
.cli
import main
, verilog
8 from singlepipe
import (ControlBase
, SimpleHandshake
, PassThroughStage
)
9 from multipipe
import CombMuxOutPipe
10 from multipipe
import PriorityCombMuxInPipe
12 from fpcommon
.getop
import FPADDBaseData
13 from fpcommon
.denorm
import FPSCData
14 from fpcommon
.pack
import FPPackData
15 from fpcommon
.normtopack
import FPNormToPack
16 from fpadd
.specialcases
import FPAddSpecialCasesDeNorm
17 from fpadd
.addstages
import FPAddAlignSingleAdd
19 from concurrentunit
import ReservationStations
, num_bits
22 class FPADDBasePipe(ControlBase
):
23 def __init__(self
, width
, id_wid
):
24 ControlBase
.__init
__(self
)
25 self
.pipe1
= FPAddSpecialCasesDeNorm(width
, id_wid
)
26 self
.pipe2
= FPAddAlignSingleAdd(width
, id_wid
)
27 self
.pipe3
= FPNormToPack(width
, id_wid
)
29 self
._eqs
= self
.connect([self
.pipe1
, self
.pipe2
, self
.pipe3
])
31 def elaborate(self
, platform
):
32 m
= ControlBase
.elaborate(self
, platform
)
33 m
.submodules
.scnorm
= self
.pipe1
34 m
.submodules
.addalign
= self
.pipe2
35 m
.submodules
.normpack
= self
.pipe3
40 class FPADDMuxInOut(ReservationStations
):
41 """ Reservation-Station version of FPADD pipeline.
43 * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
44 * 3-stage adder pipeline
45 * fan-out on outputs (an array of FPPackData: z,mid)
47 Fan-in and Fan-out are combinatorial.
49 def __init__(self
, width
, num_rows
):
51 self
.id_wid
= num_bits(width
)
52 self
.alu
= FPADDBasePipe(width
, self
.id_wid
)
53 ReservationStations
.__init
__(self
, num_rows
)
56 return FPADDBaseData(self
.width
, self
.id_wid
)
59 return FPPackData(self
.width
, self
.id_wid
)