src/ieee754/fpadd/test/test_add64.py

   1 # FIXME: This file is on the pytest ignore list in pyproject.toml because it has borked imports
   2 from nmigen import Module, Signal
   3 from nmigen.compat.sim import run_simulation
   4 from operator import add
   5
   6 from nmigen_add_experiment import FPADD
   7
   8 import sys
   9 import atexit
  10 from random import randint
  11 from random import seed
  12
  13 from unit_test_double import (get_mantissa, get_exponent, get_sign, is_nan,
  14                                 is_inf, is_pos_inf, is_neg_inf,
  15                                 match, get_case, check_case, run_fpunit,
  16                                 run_edge_cases, run_corner_cases)
  17
  18
  19 def testbench(dut):
  20     yield from check_case(dut, 0, 0, 0)
  21     yield from check_case(dut, 0x3FF0000000000000, 0x4000000000000000,
  22                                0x4008000000000000)
  23     yield from check_case(dut, 0x4000000000000000, 0x3FF0000000000000,
  24                                0x4008000000000000)
  25     yield from check_case(dut, 0x4056C00000000000, 0x4042800000000000,
  26                                0x4060000000000000)
  27     yield from check_case(dut, 0x4056C00000000000, 0x4042EA3D70A3D70A,
  28                                0x40601A8F5C28F5C2)
  29
  30     count = 0
  31
  32     #regression tests
  33     stimulus_a = [0x3ff00000000000c5, 0xff80000000000000]
  34     stimulus_b = [0xbd28a404211fb72b, 0x7f80000000000000]
  35     yield from run_fpunit(dut, stimulus_a, stimulus_b, add)
  36     count += len(stimulus_a)
  37     print (count, "vectors passed")
  38
  39     yield from run_corner_cases(dut, count, add)
  40     yield from run_edge_cases(dut, count, add)
  41
  42
  43 if __name__ == '__main__':
  44     dut = FPADD(width=64, single_cycle=False)
  45     run_simulation(dut, testbench(dut), vcd_name="test_add64.vcd")
  46